A die attach film structure includes a dicing film, an insulating adhesion layer including an upper surface and a lower surface opposite the upper surface, the lower surface of the insulating adhesion layer contacting an upper surface of the dicing film and including an insulating filler, and a conductive adhesion layer contacting an upper surface of the insulating adhesion layer and including a conductive filler.

A semiconductor package may include a first semiconductor die having a first width; a second semiconductor die on the first semiconductor die, the second semiconductor die having a second width that is smaller than the first width; and a mold layer at least partially covering a side surface of the second semiconductor die, and a top surface of the first semiconductor die, wherein the first semiconductor die comprises at least one first detection pattern, the at least one first detection pattern being on the top surface of the first semiconductor die and in contact with a bottom surface of the mold layer.

Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a metal-to-metal bond and a heat dissipation feature over the first die. The heat dissipation feature includes a thermal base over the first die and surrounding the second die, wherein the thermal base is made of a metal; and a plurality of thermal vias on the thermal base; and an encapsulant over first die and surrounding the second die, surrounding the thermal base, and surrounding the plurality of thermal vias.

A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

A semiconductor package and a manufacturing method thereof are provided. A die stack in the semiconductor package includes a photonic die and an electronic die stacked on the photonic die by a face-to-face manner. A convex lens is disposed at a back surface of the electronic die, and is formed in an oval shape, such that optical beams can be collimated to have circular beam shape, as passing through the convex lens. In some embodiments, the semiconductor package includes more of the die stacks, and includes an interposer lying below the die stacks. In these embodiments, tilted reflectors are formed in the photonic dies and the interposer, to set up vertical optical paths between the interposer and the photonic dies, and lateral optical paths in the interposer. In this way, optical communication between the photonic dies can be established.

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked on one another and disposed over the semiconductor substrate. The dielectric layer cover a top surface and a side surface of the each of the plurality of semiconductor dies. The connector is disposed over a topmost one of the plurality of semiconductor dies. The passivation layer is disposed over the dielectric layer and laterally surrounds the connector, wherein, from a cross sectional view, an acute angle is included between an outermost side surface of the passivation layer and a bottom surface of the passivation layer.

According to one embodiment, a semiconductor device includes: a circuit board; a first semiconductor chip mounted on a face of the circuit board; a resin film covering the first semiconductor chip; and a second semiconductor chip having a chip area larger than a chip area of the first semiconductor chip, the second semiconductor chip being stuck to an upper face of the resin film and mounted on the circuit board. The resin film entirely fits within an inner region of a bottom face of the second semiconductor chip when viewed in a stacking direction of the first and second semiconductor chips.