Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second die and the third die having a first surface and an opposing second surface, wherein the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die and the third die, the first material having a non-planar surface; and a layer on and in physical contact with the non-planar surface of the first material and with the second surfaces of the second die and the third die, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K).

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die having a first surface, an opposing second surface, and side surfaces between the first surface and the second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die, and wherein the side surfaces of the second die are scalloped. In some embodiments, side surfaces of the second die may include a protective coating material, where the protective coating material includes an alkyl silane, a fluoroalkyl silane, a thiol, a phosphonic acid, an alkanoic acid, a siloxane, a silazane, a polyolefin, or a fluorinated polymer. In some embodiments, a microelectronic assembly may further include a dielectric material around a plurality of second dies and the dielectric material does not have an interface seam.

A package structure and a forming method thereof are disclosed. In the package structure, two adjacent first chips arranged in a row direction are interconnected through a first wiring, two adjacent first chips arranged in a column direction are interconnected through a second wiring, and lengths of the first wiring and the second wiring are the same, so that two adjacent first chips can be interconnected in both the row direction and the column direction, thereby increasing connection channels and enhancing the bandwidth. In addition, since the lengths of the first wiring and the second wiring are the same, rates for various same or different communications or data transmissions between the two adjacent first chips arranged in rows and columns can remain consistent or vary slightly in the row direction and the column direction, thereby improving performance of the package structure.

A semiconductor package includes a base chip, a plurality of semiconductor chips stacked on the base chip, a cover chip on the plurality of semiconductor chips, adhesive layers below the cover chip and each of the plurality of semiconductor chips, and an encapsulant on the base chip and at least partially surrounding the plurality of semiconductor chips and the cover chip. The plurality of semiconductor chips includes at least one first semiconductor chip adjacent to the base chip, and at least one second semiconductor chip adjacent to the cover chip. The at least one second semiconductor chip has a second thickness smaller than a first thickness of the at least one first semiconductor chip. A width of each of the plurality of semiconductor chips is smaller than a width of the base chip, in a horizontal direction.

A semiconductor module includes a first logic chip including a first surface and a second surface parallel to a first direction and a second direction, a first semiconductor chip including a third surface and a fourth surface, arranged on the second surface, and connected to the first logic chip, and a semiconductor cube arranged on the fourth surface, the semiconductor cube including a plurality of second semiconductor chips stacked in the first direction. The second semiconductor chip includes a first inductor arranged in a third direction perpendicular to the first and second directions, and the first semiconductor chip includes a plurality of routers and a second inductor arranged parallel to the fourth surface. The plurality of circuits in the first logic chip and the plurality of circuits in the first semiconductor chip are connected using the plurality of routers, and enable contactless communication with the plurality of second semiconductor chips.

A semiconductor module includes a first logic chip including a first surface and a second surface parallel to a first direction and a second direction, a first semiconductor chip including a third surface and a fourth surface, arranged on the second surface, and connected to the first logic chip, and a semiconductor cube arranged on the fourth surface, the semiconductor cube including a plurality of second semiconductor chips stacked in the first direction. The second semiconductor chip includes a first inductor arranged in a third direction perpendicular to the first and second directions, and the first semiconductor chip includes a plurality of routers and a second inductor arranged parallel to the fourth surface. The plurality of circuits in the first logic chip and the plurality of circuits in the first semiconductor chip are connected using the plurality of routers, and enable contactless communication with the plurality of second semiconductor chips.

A semiconductor package may include a base chip, a semiconductor chip stack including a plurality of semiconductor chips sequentially stacked on the base chip, a plurality of connection bumps below the base chip, and an encapsulant covering a side surface of the first semiconductor chip and side surfaces of each of the plurality of second semiconductor chips on the base chip, wherein, on at least one side of the semiconductor chip stack, the encapsulant includes a portion in which a width thereof in a horizontal direction increases as the encapsulant being away from the base chip in a vertical direction.

A method includes forming a conductive pad over a substrate, forming a multi-layer passivation structure on the conducive pad, patterning a top portion of the multi-layer passivation structure to form a first opening, forming a mask film on sidewall surfaces of the patterned top portion of the multi-layer passivation structure, after the forming of the mask film, performing a first etching process to remove a portion of the multi-layer passivation structure directly under the first opening to form a second opening, after the performing of the first etching process, selectively removing the mask film, performing a second etching process to remove a portion of the multi-layer passivation structure directly under the second opening, thereby forming a third opening exposing the conductive pad, and forming a bonding structure in the third opening, where an etchant of the second etching process is different than an etchant of the first etching process.

A semiconductor package according to some embodiments includes: a first semiconductor die; a plurality of first connection members on the first semiconductor die; a second semiconductor die on the plurality of first connection members; an insulating member spaced apart from the first semiconductor die between the first semiconductor die and the second semiconductor die and that covers at least a portion of a lower surface of the second semiconductor die and the plurality of first connection members; and a molding material that covers at least a portion of the second semiconductor die and is between the first semiconductor die and the second semiconductor die.

An electronic package includes a redistribution wiring layer having redistribution wiring with a redistribution pad, and a bonding pad on the redistribution pad of the redistribution wiring. The bonding pad includes first, second, and third plating patterns. The first plating pattern is on the redistribution pad, and the first plating pattern includes a first material. Moreover, the first plating pattern has an inclined sidewall so that a diameter of the first plating patter decreases with increasing distance from the redistribution pad so that a first diameter of the first plating pattern adjacent the redistribution pad is greater than a second diameter of the first plating pattern spaced apart from the redistribution pad. The second plating pattern is on the first plating pattern, and the second plating pattern includes a second material different than the first material. The third plating pattern is on the second plating pattern, and the third plating pattern includes a third material different than the second material. Moreover, the second and third plating patterns have a same diameter that is no greater than the second diameter of the first plating pattern.