A continuous or cyclic etching method for etching a metal carbide over a metal nitride is disclosed. The etching method includes the following steps: supplying plasma that is generated from a gas mixture that contains N.sub.2 and H.sub.2 and does not contain halogen gases including fluorine, chlorine, bromine, and iodine to a surface of metal carbide on at least a part of the surface, to modify the surface of metal carbide, and removing the modified surface on metal carbide by ion irradiation or by heating.

A method of fabricating a pixel array substrate includes forming a semiconductor layer on a substrate, forming a metal layer stack on the semiconductor layer, forming a photoresist pattern on the metal layer stack, and removing part of the metal layer stack and the semiconductor layer not covered by the photoresist pattern at one time using a dry etching process to form a source, a drain, and a semiconductor pattern of an active device. The metal layer stack includes a first titanium layer, an aluminum layer, and a second titanium layer. The semiconductor pattern has a groove located between the source and the drain. The source and the drain respectively have a source edge and a drain edge opposite to each other, which defines two opposite side walls of the groove respectively. A pixel array substrate produced by using the method of fabricating the pixel array substrate is also disclosed.

Provided is an etching method. The etching method includes loading a substrate into a process chamber, wherein the process chamber includes a first chamber part and a second chamber part, and the substrate is loaded into the second chamber part, supplying high-density gas plasma to the first chamber part, supplying ultra-low electron temperature plasma to the second chamber part using at least a portion of the high-density gas plasma, adsorbing radicals of the ultra-low electron temperature plasma to a surface of the substrate, and applying a bias to the substrate to accelerate at least one of ions or electrons of the ultra-low electron temperature plasma so as to collide with the substrate.

The present disclosure provides a semiconductor capacitor. The semiconductor capacitor includes a first conductive layer, a second conductive layer and a dielectric layer. The dielectric layer is located between the first conductive layer and the second conductive layer, and the first conductive layer and/or the second conductive layer are performed a plasma treatment to remove impurities therein and replace the impurities with nitrogen atoms. In addition, a method of forming a semiconductor capacitor is also disclosed.

A method of processing metal-containing features in a semiconductor substrate where the metal-containing feature comprises a sidewall normal to the major surface plane of the semiconductor substrate, and a top surface having a hard mask cap layer on the top surface is treated by directing an oxidizing gas cluster ion beam (GCIB) at the major surface plane with a first irradiation angle between the gas cluster ion beam and the major surface plane of from 5 to 85 to selectively oxidize at least a portion of the metal-containing material feature to form an oxidized metal layer. The semiconductor substrate is then treated by dry plasma etching with a reactive ion etching (RIE) process to remove the oxidized metal layer to provide size adapted metal-containing features.

The present invention relates to methods of delayering a semiconductor integrated circuit die or wafer. In at least one aspect, the method includes exposing a die or wafer to plasma of an etching gas and detecting exposure of one or more metal layers within the die. In one aspect of the invention, the plasma of the etching gas is non-selective and removes all materials in a layer at about the same rate. In another aspect of the invention, two different plasmas of corresponding etching gases are employed with each plasma of the etching gas being selective, thus necessitating the sequential use of both plasmas of corresponding etching gases to remove all materials in a layer.

A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.

Barrier-free interconnects and methods of fabrication thereof are disclosed herein. An exemplary interconnect structure has a conductive line disposed over a conductive via. The conductive line has a first conductive plug disposed in a first dielectric layer, and the first conductive plug includes an electrically conductive non-metal material, such as graphite. The conductive via includes a second conductive plug disposed in a second dielectric layer, and the second conductive plug includes a metal material, such as tungsten, ruthenium, molybdenum, or combinations thereof. The first conductive plug physically contacts the second conductive plug and the second dielectric layer. The second conductive plug physically contacts the second dielectric layer. Spacers (which are insulators) may be disposed between sidewalls of the first conductive plug and the first dielectric layer. The spacers may further be disposed between the first dielectric layer and the second dielectric layer.

A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

An etching method includes: providing a substrate having a film and a patterned mask on the film; forming a silicon-containing layer including silicon, carbon, and nitrogen on the substrate using a precursor gas containing silicon; and performing a plasma etching on the film. The substrate is placed under a depressurized environment for a time period from a start time point of the step of forming the silicon-containing layer on the substrate to an end time point of the step of performing the plasma etching on the film.