Patent classifications
H10P50/267
PROCESSING SOLUTION, METHOD FOR MANUFACTURING PROCESSING SOLUTION, METHOD FOR PROCESSING SUBSTRATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
There are provided a processing solution containing an alkali compound, water, and a corrosion inhibitor, in which the amount of dissolved oxygen one week after the preparation of the processing solution is 0.2 mg/L or more and 1.5 mg/L or less, and the corrosion inhibitor is at least one selected from the group consisting of N,N-diethylhydroxylamine, 1-thioglycerol, 1-amino-4-methylpiperazine, carbohydrazide, methylethylketoxime, erythorbic acid, and salts thereof, a method for manufacturing the processing solution, and a method for processing a substrate and a method for manufacturing a semiconductor device using the processing solution.
Cut metal gate processes
A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
Methods and systems for dry etching
Methods and systems for dry etching are disclosed. The methods and systems use a showerhead with a perforated plate. The perforated plate includes a primary solid zone having no holes; a first annular zone comprising a first plurality of holes with a first total hole area; a secondary solid zone having no holes; a second annular zone comprising a second plurality of holes with a second total hole area; a third annular zone comprising a third plurality of holes with a third total hole area; and a fourth annular zone comprising a fourth plurality of holes with a fourth total hole area. The third total hole area is greater than the first total hole area and less than the second total hole area, and the fourth total hole area is greater than the second total hole area. Dry etched wafers using these systems have improved edge uniformity and improved yield.
Method of isolating the chamber volume to process volume with internal wafer transfer capability
Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a lid plate seated on the chamber body. The lid plate may define a plurality of apertures. The systems may include a plurality of lid stacks. The systems may include a plurality of substrate supports. The systems may include a plurality of peripheral valves. Each peripheral valve may be disposed in one of the processing regions. Each peripheral valve may include a bottom plate coupled with the chamber body. The peripheral valve may include a bellow. The bellow may be coupled with the bottom plate. The peripheral valve may include a sealing ring having a body defining a central aperture. A bottom surface of the body may be coupled with the bellow. The body may define a recess having a diameter greater than that of a support plate of a substrate support.
Manufacturing method of semiconductor device
Increasing in a contact-resistance between a trench gate lead-out electrode and a gate lead-out contact member is suppressed. It is assumed that a natural oxidation film is formed in the polysilicon film when the trench gate lead-out electrode is formed. In case of the natural oxidation film is formed, a desired etching process is performed so that the natural oxidation film does not protrude beyond the upper surface of the trench gate lead-out electrode.
METHOD FOR CLEANING A CHAMBER
A method for cleaning a plasma processing chamber comprising one or more cycles is provided. Each cycle comprises performing an oxygen containing plasma cleaning phase, performing a volatile chemistry type residue cleaning phase, and performing a fluorine containing plasma cleaning phase.
METHOD FOR FORMING INTERCONNECT STRUCTURE
A method for forming an interconnect structure includes filling a hole through a dielectric layer with ruthenium using a deposition-etch-deposition (DED) process, forming a ruthenium layer over the dielectric layer, and forming a conductive feature from the ruthenium layer with a subtractive process. One or more etch steps of the DED process remove isolated ruthenium nuclei deposited over the dielectric layer by deposition steps of the DED process.
SELECTIVE MATERIAL REMOVAL WITH ANGULAR BEAM
Methods of filling a gap in a semiconductor substrate are described. A first material is formed on the substrate and in a gap formed in the substrate surface. The substrate is exposed to an angular etching process to remove the first material from the field of the substrate and a top portion of the sidewalls of the gap, leaving the first material in the bottom of the gap.
Plasma processing method
An object of the present invention is to provide a highly controllable plasma processing method capable of selectively removing a metal-containing layer. In the plasma processing method for plasma etching a metal-containing film formed on a formed pattern and covered with a carbon-containing film, after the carbon-containing film is removed, the metal-containing film is removed by etching with radicals generated from plasma.
SEMICONDUCTOR DEVICE WITH ELECTRODE HAVING STEP-SHAPED SIDEWALL AND METHOD OF PREPARING THE SAME
A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, arranged from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.