A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.

A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.

A semiconductor device includes: a baseplate; an insulating substrate on the baseplate; a semiconductor element on the insulating substrate; a case bonded to the baseplate by an adhesive, the case surrounding a space in which the semiconductor element is positioned; and an encapsulating material filling the space surrounded by the case, in which, the case includes a claw, the claw includes: a protrusion protruding from an inner wall surface of the case; and a hook inclined from the protrusion, a space being sandwiched between the hook and the inner wall surface of the case.

An encapsulated integrated circuit includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. Within the encapsulation material, a phononic bandgap structure is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

An object is to provide a technique that improves the moisture uptake resistance of a semiconductor device. A semiconductor device includes a resin insulating sheet, a heat spreader provided on the resin insulating sheet, a semiconductor element mounted on the heat spreader, a lead frame having one end portion thereof connected to the semiconductor element, a first resin body that seals the resin insulating sheet, the heat spreader, the semiconductor element, and the one end portion of the lead frame with a rear surface of the resin insulating sheet being exposed, and a second resin body that seals the first resin body with the rear surface of the resin insulating sheet being exposed.

A semiconductor device includes: a first terminal and a second terminal; a first conductive member that is electrically connected to the first terminal; a semiconductor chip that is provided on the first conductive member; a second conductive member that is provided on the semiconductor chip and electrically connected to the second terminal; a first insulator that is provided on the second conductive member and covers the semiconductor chip; a conductive plate that is provided on at least a part of the first insulator; and a post that is electrically connected to the conductive plate and extends along a side surface of the first insulator.