There are provided a resin composition for semiconductor sealing, an underfill, a mold resin, and a semiconductor package that exhibit an excellent low dielectric property by a non-conventional new approach. A resin composition for semiconductor sealing according to an embodiment of the present invention is a resin composition for semiconductor sealing containing a thermosetting resin, a curing agent, an inorganic filler, and hollow resin particles, in which the hollow resin particles are contained in the resin composition for semiconductor sealing in an amount of 1% by weight to 50% by weight.

The present disclosure provides an electronic device including a first electronic unit, a second electronic unit, a circuit layer, a protection layer, and a flexible member. The first electronic unit is electrically connected to the second electronic unit through the circuit layer. The protection layer is disposed corresponding to the first electronic unit and the second electronic unit, and the protection layer has an opening. At least a portion of the flexible member is disposed in the opening. The protection layer has a first Young's modulus, the flexible member has a second Young's modulus, and the first Young's modulus is greater than the second Young's modulus.

Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.

A device structure may be provided by: forming semiconductor devices and metal interconnect structures formed within dielectric material layers over a semiconductor substrate; forming metal pads in a topmost layer of the dielectric material layers; forming a passivation layer stack including a first dielectric diffusion barrier layer, a silicate glass layer, a second dielectric diffusion barrier layer, and a polymer layer; forming openings through the passivation layer stack over the metal pads; forming die bump structures on the metal pads; and dicing a wafer including the passivation layer stack, the dielectric material layers, and the semiconductor substrate along dicing channels into a plurality of semiconductor dies.

A package structure according to the present disclosure includes a package substrate, an interposer bonded to the package substrate, a first die and a second die bonded to the interposer by way of micro bumps, an underfill surrounding the micro bumps, disposed between the first die and the interposer as well as between the second die and the interposer, a metal layer interfacing the interposer, the underfill, sidewalls of the first die, and sidewalls of the second die, a molding material over the metal layer, and a thermal interface material disposed over the molding material, the metal layer, the first die, and the second die.

A semiconductor package that includes a first redistribution structure; a logic die on the first redistribution structure; a plurality of conductive posts on the first redistribution structure, the plurality of conductive posts being laterally next to the logic die; a second redistribution structure on the logic die and the plurality of conductive posts; and a memory package on the second redistribution structure. The memory package includes a plurality of first bumps; a plurality of second bumps laterally next to the plurality of first bumps; an interposer on the plurality of first bumps, the interposer defining a through opening through the interposer; a heat dissipating structure on the plurality of second bumps, the heat dissipating structure being in the through opening; and a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure.

A semiconductor package may include: a redistribution structure; a semiconductor chip on the redistribution structure; and a molding film around the semiconductor chip. The molding film may include: a first molding layer having a first dielectric constant; and a second molding layer having a second dielectric constant that is smaller than the first dielectric constant.

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.