A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

A semiconductor package includes: a support substrate; a first semiconductor chip on the support substrate, the first semiconductor chip including one or more first chip pads; a second semiconductor chip spaced apart from the first semiconductor chip, the second semiconductor chip including one or more second chip pads; a third semiconductor chip on the first semiconductor chip and the second semiconductor chip, the third semiconductor chip comprising one or more third chip pads; one or more first conductive structures on the one or more first chip pads; one or more second conductive structures on the one or more second chip pads; and a redistribution layer on the one or more first conductive structures, the one or more second conductive structures, and the one or more third chip pads.

According to some example embodiments, a semiconductor package includes a first redistribution layer (RDL) including a first redistribution wiring structure, a substrate on the first RDL and including a wiring structure and having a rectangular ring shape, a semiconductor chip on the first RDL and in a space defined by the substrate, a heat dissipation block between the semiconductor chip and the substrate on the first RDL, a molding member on the first RDL and covering sidewalls of the semiconductor chip and the heat dissipation block and an inner sidewall of the substrate, and a second RDL on the semiconductor chip, the heat dissipation block, the substrate and the molding member and including a second redistribution wiring structure. A planar area of the heat dissipation block is greater than a planar of the semiconductor chip.

A semiconductor package may include: a package substrate; a base semiconductor chip above the package substrate, the base semiconductor chip including a base pad in contact with the package substrate; at least one stacked semiconductor chip above the base semiconductor chip, the at least one stacked semiconductor chip including a chip pad connected to the package substrate; and an organic layer between the package substrate and the at least one stacked semiconductor chip in a first direction perpendicular to a surface of the package substrate; at least one connection structure in the organic layer, the at least one connection structure connecting the package substrate and the chip pad of the at least one stacked semiconductor chip, wherein the at least one connection structure includes a filling layer and a surface layer surrounding at least a portion of the filling layer.

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive element, an active chip, an encapsulation layer, another redistribution layer, and a conductive terminal. The conductive element, the active chip, and the encapsulation layer are disposed on the redistribution layer and the encapsulation layer surrounds the conductive element and the active chip. The another redistribution layer is disposed on the conductive element, the active chip and the encapsulation layer and electrically connected to the redistribution layer through the conductive element.

A packaging structure and methods of forming the same are described. In some embodiments, the structure includes a semiconductor die and an RDL disposed over the semiconductor die. The RDL includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a conductive feature. The conductive feature includes a first portion disposed in the first dielectric layer and a second portion disposed in the second dielectric layer. The RDL further includes a first functional layer disposed between the first dielectric layer and the first portion of the conductive feature and a first n-type insulating layer disposed between the first functional layer and the first portion of the conductive feature. The first n-type insulating layer has a higher concentration of negative ions than the first functional layer.

Implementations described herein relate to various semiconductor device assemblies. In some implementations, an apparatus includes a first integrated circuit die conjoined with a second integrated circuit die in a stack of integrated circuit dies, where the first integrated circuit die includes an end region that extends beyond an edge of the second integrated circuit die. The apparatus includes an interconnect structure that is conjoined with the end region and is electrically coupled to integrated circuitry of the first integrated circuit die and a casing that encapsulates at least a portion of the interconnect structure, at least a portion of the first integrated circuit die, and at least a portion of the second integrated circuit die. The apparatus includes an electrical trace that is conjoined with a surface of the casing, is disposed along a contour of the casing, and is electrically coupled to the interconnect structure.

An integrated circuit includes a first semiconductor die having first memory circuits and a second semiconductor die having second memory circuits, the second memory circuits having a write latency shorter than that of the first memory circuits. The first semiconductor die and the second semiconductor die are interconnected by interconnections formed by wafer-level or chip-level bonding between the first and second semiconductor dies. The second semiconductor die includes an on-chip control circuit that controls operations of the first memory circuits and the second memory circuits to transfer data between the first memory circuits and the second memory circuits.

Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

A semiconductor package includes a semiconductor chip on a redistribution substrate and including a body, a chip pad on the body, and a pillar on the chip pad, a connection substrate including base layers and a lower pad on a bottom surface of a lowermost one of the base layers, a first passivation layer between the semiconductor chip and the redistribution substrate, and a dielectric layer between the redistribution substrate and the connection substrate. The first passivation layer and the dielectric layer include different materials from each other. A bottom surface of the pillar, a bottom surface of the first passivation layer, a bottom surface of a molding layer, a bottom surface of the lower pad, and a bottom surface of the dielectric layer are coplanar with each other.