Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

A method of manufacturing a semiconductor package includes: forming via holes through an insulating layer to expose a redistribution conductor; forming a preliminary seed layer extending along the insulating layer and an inner surface of the via holes; forming a first photoresist layer on the preliminary seed layer which exposes first partial surfaces of the preliminary seed layer within the via holes; forming under-bump metal (UBM) vias in the via holes; forming a second photoresist layer by removing a partial region of the first photoresist layer; forming UBM pads covering the UBM vias and the second partial surfaces of the preliminary seed layer, each of the UBM pads has a convex surface protruding on a side facing away from a corresponding one of the UBM vias; removing the second photoresist layer and a partial region of the preliminary seed layer; and attaching a solder ball on the UBM pads.

A semiconductor package includes a first substrate including a first interconnection structure, a first semiconductor chip, a second semiconductor chip, a second substrate, a molding layer between the first substrate and the second substrate, a plurality of conductive bumps that electrically connect the first interconnection structure to a first chip pad on a second surface of the first semiconductor chip that is opposite to the first surface of the first semiconductor chip, and a plurality of conductive wires that electrically connect the first interconnection structure to a second chip pad on a second surface of the second semiconductor chip that is opposite to the first surface of the second semiconductor chip.

In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.

A light-emitting assembly with higher connection tolerances in manufacture includes a substrate, a light-emitting diode on the substrate, a transparent electrode, and a wire connected to the transparent electrode. The substrate includes a driving circuit connected to the light-emitting diode. The light-emitting diode includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, the first electrode receiving the first driving signal. transparent electrode is connected to the second electrode. An orthographic projection area of the transparent electrode on the substrate is larger than an orthographic projection area of the second electrode on the substrate allowing less criticality in the alignment of signal wires for receiving the second driving signal. The light-emitting diode is configured to emit source light according to the first driving signal and the second driving signal.

An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.

Disclosed are semiconductor packages. A semiconductor package may include a first die encapsulated by a mold, and a second die directly on the mold. One or more conductive posts may be formed in the mold. A frontside redistribution layer (RDL) may be provided on a lower surface of the mold. Electrical signals between the first and second dies may be carried through the posts and the frontside RDL. There is no need for backside RDL and backside ball grid array. This can significantly reduce the height of the semiconductor package.

A fan-out wafer-level packaging (FOWLP) unit having a substrate, at least one chip, a dielectric layer, at least one conductive circuit, and an outer protective layer is provided. The chip includes a die, chip conductive circuits, a chip dielectric layer, chip bonding pads, a first chip surface, and a second chip surface. The die is electrically connected with the outside through the die pad. The conductive circuits are formed by a metal paste filled into at least one slot of the dielectric layer and grinding of the metal paste. The conductive circuits form a bonding pad in each of openings of the outer protective layer. The chip is electrically connected to the outside through the bonding pads located around a chip area on the second chip surface of the chip. Thereby problems of the FOWLP module available now including higher manufacturing cost and less environmental benefit can be solved.

A method of forming a semiconductor device includes the following steps. A die and a first through via aside the die are formed. An encapsulant is formed to encapsulate the die and the first through via, wherein the encapsulant is physically connected to a sidewall of the first through via and a sidewall of the die. A warpage controlling layer is formed over the encapsulant and the die. A first conductive connector is formed on the first through via to electrically connect to the first through via.

A workpiece handling apparatus includes a workpiece chuck, and a robotic device. The workpiece chuck is for holding a workpiece thereon, wherein the workpiece chuck includes a porous supporting platform, a gas permeable buffer layer covering a supporting surface of the porous supporting platform, and a vacuum system in gas communication with the porous supporting platform and the gas permeable buffer layer. The robotic device is movably disposed over the workpiece chuck for picking up the workpiece and placing the workpiece on the gas permeable buffer layer.