This method includes: generating a backscattered-electron image of a multilayered structure (400) including a plurality of patterns formed in a plurality of layers by a scanning electron microscope (50); classifying a plurality of regions of a virtual multilayered structure (300) including a CAD pattern created from design data of the plurality of patterns into a plurality of groups according to CAD pattern arrays in a depth direction of the virtual multilayered structure (300); performing a matching between at least one of the plurality of patterns on the backscattered-electron image and a corresponding CAD pattern; calculating a brightness index value of a region on the backscattered-electron image corresponding to a region belonging to each group; and determining that there is a pattern defect in the region on the backscattered-electron image when the brightness index value is out of a standard range.

A defect density calculation method according to one embodiment of the present disclosure is a method of calculating a temporal change of the defect density distribution in a semiconductor layer. The method includes calculating the temporal change of the defect density distribution on the basis of an arithmetic function using at least the activation energy of a detect included in the semiconductor layer, the processing temperature of the semiconductor layer, and the processing time of the semiconductor layer as arguments.

A solder reflow system that includes a vacuum chamber and a sample chuck in the vacuum chamber to support a semiconductor wafer to be processed. The solder reflow system further include a heating element coupled to the vacuum chamber and configured to heat the semiconductor wafer, a thermocouple connected to the sample chuck to measure a temperature of the semiconductor wafer, a pyrometer positioned to detect an optical signal from the semiconductor wafer to estimate the temperature of the semiconductor wafer. The control system is configured to control the heating element to heat the semiconductor wafer, obtain one or more measurements of the temperature of the semiconductor wafer from the thermocouple and one or more estimates of the temperature of the semiconductor wafer from the pyrometer during the heating of the semiconductor wafer, and determine a modification of the heating of the semiconductor wafer based on the obtained measurements.

A substrate processing apparatus includes: a substrate transfer controller that determines a placement condition of the substrate holder and a substrate placement position on the substrate holder based on a model, a substrate transfer position setting value, and a substrate holder setting value from the film thickness measurement result, and operates the substrate transfer device; an eccentricity status analysis unit that analyzes an eccentric state from a film thickness variation state; a learning function unit that updates the model based on the eccentric state; and an optimization function unit that updates the placement condition of the substrate holder and the substrate placement position on the substrate holder based on the updated model, the substrate transfer position setting value, and the substrate holder setting value.

Methods of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.

A method for performing an inline detection and repair of a defect on a substrate or interposer that does not destroy the substrate or interposer. The method is performed in the manufacturing area in separate platforms or a single platform. In some embodiments, the method may include detecting a defect on a panel in line to a panel level packaging process using an electron beam to image at least a portion of a surface of the panel, identifying a type of the defect, and repairing the defect on the panel based on the type of the defect in line with the panel level packaging process using a material removal process to remove material to fix a defect or using the electron beam in conjunction with a precursor gas to deposit material to fix a defect. The material removal process may include a plasma beam or an ion beam.

A method tests the stress robustness of a semiconductor substrate. The method includes: forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate or on a native oxide layer that is interposed on the surface; cooling the semiconductor substrate and the nitride layer; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas, which includes hydrogen or a hydrogen compound or both; processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800 C. and not more than 1300 C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property that is related to the formed dislocations.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.

Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.

The present disclosure relates to a tool and method for correcting a position of a wafer in a semiconductor manufacturing machine, including: a cover plate, disposed on one side that is of the chamber away from the wafer bearing apparatus, the cover plate is provided with a mounting hole; a transparent plate, installed in the mounting hole, a projection of the wafer bearing apparatus on the transparent plate is located in the transparent plate; and a first scale and a second scale, disposed on the transparent plate, the first scale extends to edges of the transparent plate along a first direction and a direction away from the first direction, the second scale extends to edges of the transparent plate along a second direction and a direction away from the second direction, and the first scale and the second scale are provided with a plurality of uniformly distributed scale lines.