A method includes bonding a second die including second feature to a first die. The first die includes a first feature. A first image of at least a portion of the first die is captured using a first image sensor disposed at a first angle that is normal to the first surface. A second image of at least a portion of the second die is captured using a second image sensor disposed at a second angle. The first and second images include at least a portion of the first feature and the second feature. At least one offset between the features are determined based on the first image and the second image. An alignment correction between the dies are determined based on the offset. One or more alignment commands are sent based on the alignment correction to a robot end effector system of an optical inspection system.

A surface scanning tool and methods of using a surface scanning tool to determine a surface shape of a tool. In embodiments, the surface scanning tool includes a laser, a detector, and a signal analysis module. The laser sends a beam of light that is reflected off a bottom surface of the tool. The detector receives the reflected beam of light and sends the reflected beam of light signals to a signal analysis module. The signal analysis module determines a surface shape of the bottom surface and triggers mitigation actions. In alternative embodiments, the surface scanning tool includes a camera and a signal analysis module. The camera takes a picture of the bottom surface of the tool and sends the image to the signal analysis module. The signal analysis module determines the surface shape of the bottom surface and triggers mitigation actions.

An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.

Disclosed systems and techniques are directed to improvement of semiconductor manufacturing. In one embodiment, the disclosed techniques include forming a deformation-accommodating layer (DAL) on a target substrate. The target substrate can include a first substrate supporting one or more manufactured features, or a second substrate. The techniques further include removing one or more portions of the DAL, causing the first substrate and the second substrate to form a composite structure, and thinning the first substrate to expose at least a subset of the one or more manufactured features, wherein the one or more portions of the DAL are removed to cause, responsive to the thinning, a deformation of the composite structure.

An apparatus and method for debonding a pair of bonded wafers are disclosed herein. In some embodiments, the debonding apparatus, comprises: a wafer chuck having a preset maximum lateral dimension and configured to rotate the pair of bonded wafers attached to a top surface of the wafer chuck, a pair of circular plate separating blades including a first separating blade and a second separating blade arranged diametrically opposite to each other at edges of the pair of bonded wafers, wherein the first and the second separating blades are inserted between a first and a second wafers of the pair of bonded wafers, and at least two pulling heads configured to pull the second wafer upwardly so as to debond the second wafer from the first wafer.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

Methods and systems for measurements of semiconductor structures based on a trained parameter conditioned measurement model are described herein. The shape of a measured structure is characterized by a geometric model parameterized by one or more conditioning parameters and one or more non-conditioning parameters. A trained parameter conditioned measurement model predicts a set of values of each non-conditioning parameter based on measurement data and a corresponding set of predetermined values for each conditioning parameter. In this manner, the trained parameter conditioned measurement model predicts the shape of a measured structure. Although a parameter conditioned measurement model is trained at discrete geometric points of a structure, the trained model predicts values of non-conditioning parameters for any corresponding conditioning parameter value. In some examples, training data is augmented by interpolation of conditioning parameters and corresponding non-conditioning parameters that lie between discrete DOE points. This improves prediction accuracy of the trained model.

According to embodiments, an inspection apparatus includes an imaging mechanism, an image acquisition circuit that extracts an outline from image data of a sample, a development circuit that generates a developed image, an outline data generation circuit that generates data of an outline point of a pattern of the developed image, an area calculation circuit that calculates an area of a region not included in the pattern in a circle centered on the outline point, an estimation circuit that calculates a resizing amount of the outline point based on the area, and a reference image generation circuit that executes a resizing process of data of the outline point based on the resizing amount and generates a reference image based on the data of the outline point subjected to the resizing process.

A method includes depositing an inter-metal dielectric (IMD) layer over a conductive line. A via opening is formed in the IMD layer and directly over the conductive line. A width of the conductive line is greater than a width of the via opening. An overlay measurement is performed. The overlay measurement includes obtaining a backscattered electron image of the via opening and the conductive line and determining an overlay between the via opening and the conductive line according to the backscattered electron image.

A wafer thickness measurement device of the present invention obtains, based on: first and second interferometer reference measurement results obtained by measuring, with an A-surface optical interferometer and a B-surface optical interferometer, a reference measurement point on a reference piece having the reference measurement point at which the reference piece has a known thickness; first and second distance meter reference measurement results obtained by measuring the reference measurement point with an A-surface distance meter and a B-surface distance meter; first and second interferometer measurement results obtained by measuring a measurement point of the wafer with the A-surface optical interferometer and the B-surface optical interferometer; and first and second distance meter measurement results obtained by measuring the measurement point with the A-surface distance meter and the B-surface distance meter, and obtains a thickness, of the wafer, at the measurement point.