Patent classifications
H10P14/2922
Rare-earth doped semiconductor material, thin-film transistor, and application
Disclosed in the present invention is a rare-earth doped semiconductor material. Compounds of two rare-earth elements R and R having different functions are introduced into an indium oxide containing material. The coupling of R element ions to an O2p orbit can effectively enhance the transfer efficiency of the rare-earth R as a photogenerated electron transfer center, such that the light stability of a device with a small amount of R doping can be achieved. Compared with single rare-earth element R doping, due to less doping, the impact on a mobility is less, such that higher mobility and light stability devices can be obtained. Further provided in the present invention is a semiconductor-based thin-film transistor, and an application.
SELECTIVE PASSIVATION AND SELECTIVE DEPOSITION
Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.
Heteroepitaxial semiconductor device and method for fabricating a heteroepitaxial semiconductor device
A heteroepitaxial semiconductor device includes a bulk semiconductor substrate, a seed layer including a first semiconductor material, the seed layer being arranged at a first side of the bulk semiconductor substrate and including a first side facing the bulk semiconductor substrate, an opposing second side and lateral sides connecting the first and second sides, a separation layer arranged between the bulk semiconductor substrate and the seed layer, a heteroepitaxial structure grown on the second side of the seed layer and including a second semiconductor material, different from the first semiconductor material, and a dielectric material layer arranged on the seed layer and at least partially encapsulating the heteroepitaxial structure, wherein the dielectric material layer also covers the lateral sides of the seed layer.
Laser irradiation apparatus, laser irradiation method, and recording medium recording program to be readable
A laser irradiation apparatus is a laser irradiation apparatus including a plurality of laser light sources, the laser irradiation apparatus including a control unit configured to perform control with regard to laser emitted from the plurality of laser light sources, in which the control unit acquires characteristic information of each of the plurality of laser light sources, and performs a predetermined process according to each piece of acquired characteristic information.
Manufacturing method of gallium nitride film
A method for manufacturing a gallium nitride film includes the steps of placing a substrate so as to face a target containing nitrogen and gallium in a vacuum chamber, supplying a sputtering gas into the vacuum chamber, supplying a nitrogen radical into the vacuum chamber, generating a plasma of the sputtering gas by application of a voltage to the target, generating a gallium ion by a collision of an ion of the sputtering gas with the target, and stopping the application of the voltage to the target and depositing gallium nitride on the substrate. The gallium nitride is generated by a reaction of the gallium ion with a nitrogen anion which is generated by a reaction of an electron in the vacuum chamber with the nitrogen radical.
IGZO thin-film transistor and method for manufacturing same
An IGZO thin-film transistor and a method for manufacturing same. The method includes: acquiring a substrate; forming an IGZO layer on the substrate by a solution process; doping V impurities on a surface of the IGZO layer by a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.
Process for direct deposition of graphene or graphene oxide onto a substrate of interest
The present invention pertains to a process for direct deposition of graphene oxide onto a substrate of interest from a gaseous source of at least one carbon precursor, using a plasma-enhanced chemical vapor deposition method. It is also directed to a device for implementing this process.
Vapor deposition of tellurium nanomesh electronics on arbitrary surfaces at low temperature
A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.
Method for preparing silicon-on-insulator
In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 , respectively, so as to realize the flatness of the silicon-on-insulator film.
Method for producing a continuous nitride layer
The invention relates to a method for obtaining a layer at least partially made of a nitride (N), first comprising the provision of a stack comprising at least one assembly of pads (1000A1-1000B4) extending from a substrate (100). Each pad comprises at least one creep section (220A1-220A5) and one crystalline section (300A1,300A5) surmounting the creep section (200A1-200A5). Then, a crystallite (510A1-510A5) is epitaxially grown on at least some of said pads until coalescence of the crystallites, so as to form a nitride layer (550A). The pads of the assembly are distributed over the substrate, such that the relative arrangement of the pads of the assembly is such that during the epitaxy of the crystallites, the progressive coalescence of the crystallites is always done between, on the one hand, a crystallite or a plurality of coalesced crystallites and, on the other hand, an isolated crystallite.