Patent classifications
H10W70/092
Lot of devices with repairable redistribution layer (RDL) design with a custom RDL
The disclosure concerns methods of forming a semiconductor device with a repairable redistribution layer (RDL) design, comprising: preparing an original repairable RDL design; forming first conductive segments of the repairable RDL design; inspecting the first conductive segments of the repairable RDL design to detect manufacturing defects; detecting at least one defect in the first conductive segments; and forming second conductive segments of the repairable RDL design according to a new custom RDL design to mitigate the negative effects of the at least one defect among the first conductive segments. The disclosure also concerns semiconductor devices with a repairable RDL design.
SEMICONDUCTOR PACKAGE HAVING INTERCONNECTABLE SUBSTRATES
A semiconductor package includes a number of different substrate sections. Each substrate section includes one or more electronic components. Additionally, each substrate section is mechanically and electrically coupled together using various conductive columns and conductive apertures. Because the substrate sections are interconnectable, a shape and/or a size of the semiconductor package is fully customizable. Additionally, a layout of the various electronic components of the semiconductor package is also fully customizable.
Packaging device including bumps and method of manufacturing the same
A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
In one example, an electronic device comprises a substrate comprising a first side and a second side opposite the first side, wherein the substrate comprises a first groove at the second side of the substrate, a first electronic component over the first side of the substrate, and a resin in the first groove. The substrate comprises a floating pad at the first side of the substrate, a second groove at the first side of the substrate, and a third groove at the first side of the substrate, wherein the floating pad is between the second groove and the third groove. Other examples and related methods are also disclosed herein.
FILL SHAPE OPTIMIZATION FOR SUBSTRATE BONDING
A method of forming a patterned metal layer on a substrate includes identifying at least one distortion zone in a design pattern of metal structures causing a Z-direction displacement of the substrate, inserting metal fill shapes as a fill pattern into the design pattern to reduce the Z-direction displacement in the at least one distortion zone, and forming the metal structures and the metal fill shapes on the substrate as the patterned metal layer. The method may further include calculating bond strength of the substrate based on the design pattern and the fill pattern and adjusting surface area of the metal fill shapes to increase the bond strength. A bonded substrate structure may then be formed by directly bonding a dielectric material of the patterned metal layer of the substrate to an additional substrate.
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package includes forming a plurality of redistribution pads including a first pad layer, a second pad layer, and a third pad layer sequentially stacked on a redistribution structure, forming a preliminary seed layer conformally extending on an upper surface of the redistribution structure, and on upper surfaces and side surfaces of the plurality of redistribution pads, forming a metal pillar on the preliminary seed layer, forming surface roughness on the metal pillar, and etching at least a portion of the preliminary seed layer exposed on the side surfaces of the plurality of redistribution pads and the upper surface of the redistribution structure to provide a seed layer between the metal pillar and one of the plurality of redistribution pads thereon.
STITCHING DEFECT REDUCTION USING GAS CLUSTER BEAM
A method of processing a substrate includes providing a substrate including a pattern of lines extending in a first direction, and reducing stitching defects by removing material from the pattern of lines using a gas cluster beam. The pattern of lines includes a first subset of lines stitched to a second subset of lines in a stitching region that includes the stitching defects. The gas cluster beam includes an azimuthal component substantially parallel to the first direction. The stitching defects may be further reduced using an additional gas cluster beam in the opposite and substantially parallel to the first direction. The method may further include exposing a first region and a second region of a photosensitive layer of the substrate to different structured actinic radiation, and forming the pattern of lines on the substrate by developing the first region and the second region.
REPAIR OF SIGNAL PATHS FOR STACKED DIE
Embodiments herein relate to ensuring the integrity of signal paths in stacked semiconductor devices. In an example implementation, a faulty signal path between die can be repaired by re-routing the path within the affected die, in a per-layer repair approach. Also disclosed are a sequential repair process for N-stacked die prior to integration, an in-field fault detection and repair technique, a proactive in-field repair technique for preemptive die maintenance, and a technique to drive select lines of repair multiplexers to provide rerouting of signal paths.
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
Provided are an electronic package and a manufacturing method thereof. A groove is formed in a carrier structure, and a circuit structure is disposed in the groove. Therefore, chips with different specifications can be used as a first electronic component and a second electronic component electrically connected to the carrier structure and the circuit structure, respectively, thereby multi-functional requirements can be met.