Disclosed aspects include a semiconductor die including a substrate having a semiconductor surface including circuitry. A top metal layer is above the semiconductor surface including top metal lines that are electrically connected through a metal stack including metal interconnects that electrically connect to the circuitry. The top metal lines are configured in a primary orientation that collectively represents at least 50% of a total length of the top metal lines in a first direction. The top metal layer includes bond pads exposed from a passivation layer. The metal features are positioned lateral to and not directly electrically connected to the top metal layer and/or are positioned on the passivation layer. At least a majority of a total area of the metal features is not over metal interconnects. The metal features have a length direction oriented in a second direction that is at least essentially perpendicular relative to the primary orientation.

A substrate includes a base plate made of an insulating material, a first electrically conductive layer disposed on a first side of the base plate, and a second electrically conductive layer disposed on a second side of the base plate. The first electrically conductive layer has a stepped surface, the stepped surface including a plurality of steps at different heights above the base plate.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 m.

A semiconductor device assembly can include a first semiconductor device comprising CMOS circuitry at a first active surface and a second semiconductor device having a footprint smaller than that of the first semiconductor device and including memory array circuitry at a second active surface hybrid-bonded to the first active surface. The assembly can further include a gapfill material directly contacting the first active surface of the first semiconductor device and having an upper surface coplanar with a back surface of the second semiconductor device, and a metallization layer disposed over the second semiconductor device and the gapfill material. The metallization layer can include conductive structures operably coupled to the second semiconductor device through back-side contacts of the second semiconductor device. The assembly can further include a plurality of bond pads disposed at an upper surface of the metallization layer and coupled to the conductive structures of the metallization layer.

A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.

A semiconductor device comprising a terminal, a semiconductor element and a sealing resin. The semiconductor element is disposed on one side of the terminal in a first direction and electrically connected to the terminal. The sealing resin covers the semiconductor element and a part of the terminal. The sealing resin has a bottom surface disposed on an opposite side to the semiconductor element with respect to the terminal in the first direction. The terminal extends beyond the bottom surface.

A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

A semiconductor arrangement includes first and second controllable semiconductor devices forming a half-bridge arrangement, each controllable semiconductor device including a control electrode and a controllable load path between a first load electrode and a second load electrode. At least one gate driver is configured to generate one or more control signals for one or more of the controllable semiconductor devices. The first controllable semiconductor device is arranged on and electrically coupled to a first lead frame of a plurality of lead frames. The second controllable semiconductor device is arranged on and electrically coupled to a second lead frame of the plurality of lead frames. The controllable semiconductor devices and the at least one gate driver are arranged in a molded package. Each lead frames is partly covered by the molded package and has at least one surface or section that is not covered by the molded package.

A semiconductor device includes a plurality of bonding pads which are constituted by an uppermost layer of a wiring layers, first and third bonding pads connected to an external power supply of the semiconductor chip, second and fourth bonding pads connected to the ground, a fifth bonding pad connected to the third bonding pad via the first inner wiring, and a sixth bonding pad connected to the fourth bonding pad via the second inner wiring, wherein there is no wiring constituting a circuit in one layer just below the uppermost layer at the first and second bonding pads, and there is a wiring constituting the circuit in the one layer just below the uppermost layer at the third to sixth bonding pads.

A device includes a high frequency chip and a dielectric material arranged between a first area radiating an electromagnetic interference signal in a first frequency range between 1 GHz and 1 THz and a second area receiving the electromagnetic interference signal. An attenuation of the dielectric material is more than 5 dB/cm at least in a subrange of the first frequency range.