A semiconductor device is provided. The semiconductor device comprises a detection circuit electrically coupled between a first node and a second node. The semiconductor device comprises a discharge circuit electrically coupled between the first node and a third node. The semiconductor device comprises a biasing circuit electrically coupled between the second node and the third node. The discharge circuit and the biasing circuit are configured to electrically conduct the first node and the second node in response to receiving a first signal from the detection circuit through a fourth node. A first voltage difference exists between the third node and the fourth node.

A package includes a first die and a second die stacked vertically over one another. A first surface of the first die facing a second surface of the second die. The first die includes an ESD protection device. The ESD protection device includes a conductive pattern adjacent to the first surface of the first die and an interconnect structure connected to the conductive pattern and extending toward a first semiconductor substrate of the first die that is opposite to the first surface of the first die.

A semiconductor device includes a substrate, a doped ring, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate in the second region and surrounds the first region. The first doped region has an opening. The second doped regions are separated from each other and located in the substrate of the opening. The contacts are electrically connected to the second doped regions. The conductive lines are connected to the contacts and a plurality of conductive layers in the first region.

A layered body contains: a first resin layer; a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which the first resin layer comprises a storage portion, and the first conductive layer is disposed within the storage portion of the first resin layer. A conductive layered body contains: a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which an adhesive layer is provided between the first conductive layer and the insulating layer, and between the insulating layer and the second conductive layer, respectively.

A layered body contains: a first resin layer; a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which the first resin layer comprises a storage portion, and the first conductive layer is disposed within the storage portion of the first resin layer. A conductive layered body contains: a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which an adhesive layer is provided between the first conductive layer and the insulating layer, and between the insulating layer and the second conductive layer, respectively.

A semiconductor device may include a substrate having a chip region and a scribe lane region, the chip region including a plurality of chips arranged in a first direction and in a second direction, the second direction crossing the first direction, the scribe lane region surrounding the chip region, a peripheral circuit structure on the substrate, the peripheral circuit structure including a transistor with a gate and an active region, a cell structure on the peripheral circuit structure, a protective layer on at least a portion of the cell structure, and a discharge structure penetrating through the cell structure in a third direction, the third direction crossing each of the first direction and the second direction, the discharge structure electrically connected to the substrate. An upper surface of the discharge structure is exposed to an outside of the cell structure.

Some embodiments relate to an integrated device, including: a resistor and capacitor structure coupled in series between a high voltage wire and a low voltage wire, the resistor and capacitor structure having a first node electrically coupled to a resistor and a capacitor; a transistor comprising a first source/drain terminal coupled to the high voltage wire, a second source/drain terminal coupled to the low voltage wire, and a gate terminal; and a diode coupled between the gate terminal and either the high voltage wire or the low voltage wire.

A semiconductor device includes a semiconductor substrate including a main chip region, a guard ring surrounding the main chip region, a moisture-proof ring surrounding the guard ring, an electrode structure in contact with the semiconductor substrate in the main chip region, and at least one metal pattern structure extending from the electrode structure to the moisture-proof ring. The at least one metal pattern structure is a connection line that grounds the moisture-proof ring.

A semiconductor device includes a semiconductor substrate including a main chip region, a guard ring surrounding the main chip region, a moisture-proof ring surrounding the guard ring, an electrode structure in contact with the semiconductor substrate in the main chip region, and at least one metal pattern structure extending from the electrode structure to the moisture-proof ring. The at least one metal pattern structure is a connection line that grounds the moisture-proof ring.

An apparatus may include a fuse coupled between a bidirectional electrostatic discharge (ESD) element and a first bond contact, the fuse is configured to receive an ESD discharge current generated between the first bond contact and a second bond contact, and the fuse is configured to blow in response to the ESD discharge current exceeding a threshold current magnitude, and a detector coupled to the bidirectional ESD element, the detector is configured to determine a state of the fuse.