A semiconductor device includes a power semiconductor element, and a molding resin sealing the power semiconductor element. In plan view, the molding resin has a rectangular shape consisting of a first side and a second side extending along a first direction, and a third side and a fourth side extending along a second direction orthogonal to the first direction. The first side is longer than the third side. The molding resin is provided with a first threaded bore and a second threaded bore, the first threaded bore and the second threaded bore penetrating the molding resin along a third direction orthogonal to the first direction and the second direction.

A semiconductor device comprises a semiconductor chip and an electrically conductive chip carrier, wherein the semiconductor chip is mounted on the chip carrier. The semiconductor device furthermore comprises an electrically conductive extension element mechanically connected to the chip carrier, wherein the extension element and the chip carrier are formed as an integral single piece. A part of the chip carrier which has the extension element is configured as an antenna.

Semiconductor chips to be singulated to individual semiconductor devices are arranged onto respective adjacent areas of a mounting substrate such as a pre-molded leadframe. The mounting substrate is made of a laminar, electrically conductive sculptured structure with molded electrically insulating material. Electrically conductive side formations in the adjacent areas of the mounting substrate include first and second pads at front and back surfaces, respectively, of the mounting substrate. The first contact pads at the front surface of the substrate include narrowed portions having side recesses. The second contact pads at the back surface of the substrate include widened portions having side extensions adjacent the side recesses. The electrically insulating material extends into the side recesses to provide anchoring formations of the insulating material to the electrically conductive sculptured structure of the mounting substrate.

Aspects of the present disclosure include systems, structures, circuits, and methods providing integrated circuit (IC) packages or modules having diagonalized leads. First and second semiconductor dies are disposed on a substrate. First and second coils are configured on the substrate for a transformer. The transformer may include a core. The leads or pins may be aligned along a diagonal of the package body, providing increased creepage. The IC packages and modules may include various types of circuits; in some examples, IC packages or modules may include a galvanically isolated gate driver or other high voltage circuit.

Disclosed in this disclosure are a pad, lead frame, and sensor packaging structure for attenuating an eddy current effect, which are applied to the field of semiconductor preparation. The pad includes a first pad component and a second pad component, where the first pad component and the second pad component are disposed on two adjacent sides of a chip placement region; and the first pad component and the second pad component are electrically connected, such that the first pad component and the second pad component surround the chip placement region on the two adjacent sides. In this disclosure, by means of arranging the pad along two adjacent sides of a chip, the formation of closed eddy current loops in a metal frame can be further reduced, thereby weakening the impact of a reversed magnetic field, and thus improving the detection sensitivity and accuracy of a sensor.

An integrated circuit package includes a leadframe with leads delimiting a center cavity. The leads of the leadframe have upper surfaces with a surface texture or finish having a first surface roughness. A drop-in die pad is installed within the center cavity. The drop-in die pad has an upper surface with a surface texture or finish having a second surface roughness that is rougher than the first surface roughness. An integrated circuit die is mounted to the upper surface of the drop-in die pad and electrical connections are formed between bonding pads of the integrated circuit die and the leads of the leadframe. An encapsulation body encapsulates the leadframe, drop-in die pad and electrical connections.

A device includes a first conductive-member which connects to a first electrode on a first face of a chip. A second conductive-member is spaced from the chip and the first conductive-member. A third conductive-member is spaced from the first and second conductive-members. A first connector connects between the second electrode and the second conductive-member. A second connector is opposed to a third electrode on the second face and connects the third electrode and the third conductive-member. A first connecting-member connects the first connector and the second face. A second connecting-member connects the first connector and the second conductive-member. The first connector includes first protruded portions protruded in a first direction from the first conductive-member to the second conductive-member. The second connecting-member is provided to correspond to each of places between the first protruded portions and the second conductive-member.

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

The present disclosure discloses a method of fabricating a semiconductor integrated circuits package with solder wettable plating and relates to a semiconductor package substrate with side wettable flank (SWF) features and a method of manufacturing thereof. In particular, the disclosure relates to leadless semiconductor devices and an associated method of manufacturing such devices. An object of the present disclosure is to provide a manufacturing technique allowing full plating of the side flanks by conventional electro-plating with an external conductive media.

An electronic device includes a conductive lead, a semiconductor die, a package structure enclosing the semiconductor die and a portion of the conductive lead, and a non-conductive die attach film extending between the conductive lead and the semiconductor die, with a lateral side of the semiconductor die extending beyond an end of the die attach film by a non-zero gap distance. A method of fabricating an electronic device includes performing a first singulation process that separates portions of a die attach film on a wafer, performing a second singulation process that separates a semiconductor die from the wafer having a portion of the die attach film, and attaching the semiconductor die to a lead frame with the die attach film extending between a prospective lead portion and the side of the semiconductor die.