A semiconductor device includes: a semiconductor element having an element main surface and an element back surface spaced apart from each other in a thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad on which the semiconductor element is mounted; a plurality of leads including at least one first lead and at least one second lead and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member and a second connecting member and configured to electrically connect the plurality of main surface electrodes and the plurality of leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the plurality of leads, and the plurality of connecting members and having a rectangular shape when viewed in the thickness direction.

A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum spacing distance is between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum spacing distance is between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum spacing distance is larger than the second minimum spacing distance.

Reliability of a semiconductor device is improved. The semiconductor device includes a clip which is electrically connected to a main-transistor source pad via a first silver paste and is connected to a lead via a second silver paste. The clip has a first part with which the first silver paste is in contact, a second part with which the second silver paste is in contact, and a third part positioned between the first part and the second part. A protruding member is formed on a surface of the main-transistor source pad, and the first part is in contact with the protruding member.

A semiconductor package assembly and an electronic device are provided. The semiconductor package assembly includes a base, a system-on-chip (SOC) package, a memory package and a silicon capacitor die. The base has a first surface and a second surface opposite the first surface. The SOC package is disposed on the first surface of the base and includes a SOC die having pads and a redistribution layer (RDL) structure. The RDL structure is electrically connected to the SOC die by the pads. The memory package is stacked on the SOC package and includes a memory package substrate and a memory die. The memory package substrate has a top surface and a bottom surface. The memory die is electrically connected to the memory package substrate. The silicon capacitor die is disposed on and electrically connected to the second surface of the base.

In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

A switching device includes: a switching element; a die pad; a gate terminal; a first power terminal integral with the die pad; and a second power terminal, the gate terminal, the first power terminal, and the second power terminal are located on a side of a first direction of the die pad, the gate terminal, the first power terminal, and the second power terminal are arranged in a second direction orthogonal to the first direction in the following order: the gate terminal, the first power terminal, and the second power terminal or the second power terminal, the first power terminal, and the gate terminal, the switching element includes a first and a second gate pad, the first gate pad is closer to the gate terminal than the second gate pad is, the second gate pad is closer to the second power terminal than the first gate pad is.

A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.

A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.

A package and method is disclosed. In one example, the package comprises a carrier comprising a component mounting area from which a tie bar extends, the tie bar being configured for being clamped by an encapsulation tool pin during encapsulation, an electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier, wherein a sidewall of the package has a step between a first vertical sidewall section and a second vertical sidewall section; wherein the first vertical sidewall section has a notch in the encapsulant and a part of the second vertical sidewall section exposes the tie bar.

A lead-wire frame structure for packaging and a sensor package structure, which are applied to the field of sensor preparation. The lead-wire frame structure comprises: a bonding-pad component and a plurality of pin components, wherein the bonding-pad component is provided with an inward recess in a plane direction of a coplane which is formed by the bonding-pad component and the plurality of pin components. In the plane direction, arc-shaped packaging interfaces for offsetting stresses are formed in an aligned manner on an inner contour of the recess and an outer contour of the recess in the bonding-pad component. In the present application, the bonding-pad component is provided with the inward recess in the plane direction, and the aligned packaging interfaces of the inner contour of the recess and the outer contour of the recess arc designed to be of arc-shaped structures, which can offset internal and external stresses.