A semiconductor device including a first epitaxial source/drain feature, a second epitaxial source/drain feature, two or more semiconductor layers electrically connected to the first and second epitaxial source/drain features, a backside source/drain contact, and a bottom dielectric layer is provided. The backside source/drain contact is disposed on one side of the first epitaxial source/drain feature, the backside source/drain contact is electrically connected to a bottom surface of the first epitaxial source/drain feature. The bottom dielectric layer is disposed on a backside of the semiconductor layers, and the bottom dielectric layer electrically isolates the backside source/drain contact from the semiconductor layers.

A device includes a channel layer, a gate structure, a first source/drain structure, a second source/drain structure, and a backside via. The gate structure surrounds the channel layer. The first source/drain structure and the second source/drain structure ate connected to the channel layer. The backside via is connected to a backside of the first source/drain structure. The backside via includes a first portion, a second portion, and a third portion. The first portion is connected to the backside of the first source/drain structure. The third portion tapers from the second portion to the first portion. A sidewall of the third portion is more inclined than a sidewall of the second portion.

There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Interconnect structures having dielectric layers with nitrogen-containing crusts and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first interconnect opening in a first interlayer dielectric (ILD) layer that exposes an underlying conductive feature, such as a source/drain, a gate, a contact, a via, or a conductive line. The method includes nitridizing sidewalls of the first interconnect opening, which are formed by the first ILD layer, before forming a first metal contact in the first interconnect opening. The nitridizing converts a portion of the first ILD layer into a nitrogen-containing crust. The first metal contact can include a metal plug and dielectric spacers between the metal plug and the nitrogen-containing crust of the first ILD layer. The method can include forming a second interconnect opening in a second ILD layer that exposes the first metal contact and forming a second metal contact in the second interconnect opening.

Provided is a semiconductor device including a MOS gate structure provided in a semiconductor substrate, including: an interlayer dielectric film which includes a contact hole and is provided above the semiconductor substrate; a conductive first barrier metal layer provided on side walls of the interlayer dielectric film in the contact hole; a conductive second barrier metal layer stacked on the first barrier metal layer in the contact hole; and a silicide layer provided on an upper surface of the semiconductor substrate below the contact hole, in which the first barrier metal layer is more dense than the second barrier metal layer, and a film thickness thereof is 1 nm or more and 10 nm or less.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a contact including a silicide overlying at least a portion of the substrate in the one or more features, which has a contact length of less than 40 Angstroms. The methods for generating a reduced contact length silicide layer includes depositing a first metal, and performing at least one thermal anneal to generate a silicide having a reduced contact length.

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.