A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Microelectronic deviceshaving at least one conductive contact structure adjacent a silicide regionare formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.

An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in a first region, and the first source/drain epitaxial feature is asymmetric with respect to a fin. The structure further includes a second source/drain epitaxial feature disposed in the first region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, and a conductive feature disposed over the first and second source/drain epitaxial features and the first dielectric feature.

The chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a first salicide layer formed on a bottom surface of the first epi layer.

In one example, a method of forming an integrated circuit includes receiving a partially formed semiconductor device over a substrate. The semiconductor device includes a semiconductor layer. A Ni.sub.xPt.sub.y layer is formed on the semiconductor layer. A Ni.sub.mPt.sub.n layer is formed on the Ni.sub.xPt.sub.y layer. The Ni.sub.xPt.sub.y layer and the Ni.sub.mPt.sub.n layer are heated, thereby forming a nickel silicide layer extending into the semiconductor layer. A remaining portion of the Ni.sub.mPt.sub.n layer is removed.

A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.