An electronic device comprising one or more blocking regions. The electronic device also comprises a source stack comprising one or more conductive materials, a source contact vertically adjacent to the source stack, and a doped semiconductive material vertically adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are vertically adjacent to the doped semiconductive material, and pillars extend through the tiers of alternating conductive materials and dielectric materials, the doped semiconductive material, and the source contact and into the source stack. The one or more blocking regions are laterally adjacent to the semiconductive material. Additional electronic devices, electronic systems, and methods are also disclosed.

A method of forming a semiconductor structure includes forming a fin structure; forming first and second source/drain trenches in the fin structure; forming first and second semiconductor material layers in the first and second source/drain trenches, respectively; and forming first and second source/drain features over the first and second semiconductor material layers in the first and second source/drain trenches, respectively. The method further includes flipping the semiconductor structure; forming a hard mask layer on a backside of the substrate; etching the hard mask layer and the substrate to form a first opening that exposes the first semiconductor material layer; forming an insulating layer on a sidewall of the first opening; removing the first semiconductor material layer to form a second opening that exposes the first source/drain feature; and depositing a conductive material in the first and second openings to form a first source/drain contact.

A method for forming a semiconductor structure includes: forming a trench in a base structure; forming a dipole metal layer in the trench, the dipole metal layer having a lateral portion formed along a sidewall of the trench and a bottom portion formed along a bottom wall of the trench; removing the lateral portion of the dipole metal layer using an etchant including at least one of a metal halide and a hydrogen halide; after removal of the lateral portion of the dipole metal layer, forming a metal silicide layer over the bottom portion of the dipole metal layer using a precursor including the metal halide; and forming a metal contact in the trench.

A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed through the top portion of the first S/D structure, and a second contact structure formed through the bottom portion of the first S/D structure. The second contact structure is electrically connected to the first contact structure.

In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

A semiconductor structure includes a source/drain feature, a gate structure disposed adjacent to the source/drain feature, a source/drain contact disposed over and electrically connected to the source/drain feature, an interlayer dielectric (ILD) layer over the source/drain feature and adjacent to the source/drain contact and the gate structure, and an air gap surrounding the source/drain contact and separating the source/drain contact from the ILD layer and the gate structure in a top view.

A device includes a gate structure, a source/drain structure, a source/drain conductor, a barrier layer, and a dielectric liner layer. The gate structure is over a semiconductor structure and includes a gate dielectric layer and at least one titanium-containing metal layer over the gate dielectric layer. The source/drain structure is adjacent the gate structure and a sidewall of the semiconductor structure. The source/drain conductor is over the source/drain structure. The barrier layer warps around the source/drain conductor. The dielectric liner layer is on a sidewall of the barrier layer. Both the dielectric liner layer and the barrier layer extend into the source/drain structure.

A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.

Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.