In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.

The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Integrated circuit structures having source or drain structures with vertical trenches having contacts therein are described. In an example, an integrated circuit structure includes a stack of nanowires above a sub-fin. An epitaxial source or drain structure is at an end of the stack of nanowires, the epitaxial source or drain structure having a trench therein. A conductive contact is in the trench and extends above the epitaxial source or drain structure, or an epitaxial layer is along sides and a bottom the trench and a conductive contact is within the epitaxial layer and extends above the epitaxial layer, where the epitaxial layer includes gallium.

A method of forming a semiconductor device includes the following steps. A first layer is provided, wherein a material of the first layer is amorphous or single crystal. A first conductive layer is directly deposited on the first layer, wherein the first conductive layer is in direct contact with the first layer, and a cross-sectional area of a grain of a material of the first conductive layer is larger than 500 nm.sup.2.

Embodiments of the present disclosure provide semiconductor devices and methods of forming the same. An exemplary semiconductor device of the present disclosure includes a first channel region disposed over a semiconductor substrate; a gate structure disposed over the first channel region; a first source/drain region disposed at a first side of the first channel region; a second source/drain region disposed at a second side of the first channel region; an interlayer dielectric layer disposed over the first channel region, the first source/drain region, and the second source/drain region; a first contact disposed in the interlayer dielectric layer and electrically coupled to the first source/drain region; and a second contact disposed in the semiconductor substrate and electrically coupled to the second source/drain region.

Disclosed are a semiconductor device based on seedless silicon (Si) source/drain contact resistance reduction and laser process technology and a method of fabricating the same. The semiconductor device includes an activated seedless Si layer formed on a substrate and at least one electrode formed on the seedless Si layer, and the seedless Si layer is crystalized through a first laser process and then activated through a second laser process.

A semiconductor device can include: a semiconductor doped region; a patterned interlayer dielectric layer located on the semiconductor doped region; an electrode structure connected to the semiconductor doped region through opening holes of the interlayer dielectric layer; a patterned metal silicide layer located on the semiconductor doped region; where the electrode structure comprises a first conductive pillar and a second conductive pillar, the first conductive pillar is connected to the metal silicide layer, and the second conductive pillar is connected to an upper surface of the semiconductor doped region; and where the first conductive pillar and the second conductive pillar are not in contact with a heavily doped region in the semiconductor doped region, and the doping concentration of the semiconductor doped region is not greater than 10.sup.18 cm.sup.3.

A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.

Semiconductor devices, manufacturing methods of the semiconductor devices, and memory systems are provided. In one aspect, a semiconductor device includes a first semiconductor structure that includes a semiconductor body, a capacitor structure, and a connection structure. The semiconductor body extends along a first direction. The capacitor structure is located on a side of the semiconductor body in the first direction and includes a first electrode layer. A first end of the connection structure in the first direction is in contact with the semiconductor body, and at least a part of a second end of the connection structure is located in the first electrode layer.