A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a well region positioned within the substrate; an isolation structure positioned in the well region; a fuse medium positioned over the well region; a gate electrode positioned over the fuse medium; a fuse doped region positioned under the fuse medium and within the well region; a source/drain region positioned adjacent to the fuse doped region; and a resistance modification doped region partially overlapping the fuse doped region. The fuse doped region and the resistance modification doped region have a first conductive type and the well region has a second conductive type different from the first conductive type.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a well region positioned within the substrate; an isolation structure positioned in the well region; a fuse medium positioned over the well region; a gate electrode positioned over the fuse medium; a fuse doped region positioned under the fuse medium and within the well region; a source/drain region positioned adjacent to the fuse doped region; and a resistance modification doped region partially overlapping the fuse doped region. The fuse doped region and the resistance modification doped region have a first conductive type and the well region has a second conductive type different from the first conductive type.

A solid state circuit breaker structure and electronic switching circuit is provided. The solid state circuit breaker structure includes a power substrate, a power die, a plurality of bond wires, and a magnetic body. The power die is mounted on the power substrate. The bond wires extend outwardly from the power die. The magnetic body is attached to the power substrate and disposed to increase a magnetic field produced by a current flowing through the bond wires and thereby produce a first inductance that produces a decrease in an overvoltage at turn off of the power die.

Provided are a semiconductor package of which yield may be improved through rescuing and a test method and a rescue method for the semiconductor package. The semiconductor package includes a base chip, a plurality of memory chips stacked on the base chip, and a deactivation controller configured to deactivate the memory chips, wherein the memory chips are classified into at least two stack-ID (SID) regions, each of the at least two SID regions includes a subset of the plurality (set number) of memory chips, and, when a fail-SID region including a failed memory chip, from among the at least two SID regions, exists, the deactivation controller is configured to deactivate all memory chips included in the fail-SID region, and activate memory chips in remaining SID regions other than the fail-SID region.

A low-voltage varistor includes a cured body of a resin composition for forming the low-voltage varistor. The resin composition includes: (A) at least one selected from carbon nanotubes and carbon aerogels; and (B) at least one selected from epoxy resin and acrylic resin.

There is provided a semiconductor device 1, comprising: a housing comprising a housing electrode 4; and at least one semiconductor chip 20 arranged within the housing; wherein the housing electrode 4 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between an interior and an exterior of the housing exceeds a threshold differential pressure or a temperature at the deformable portion exceeds a threshold temperature, so as to transform the housing from a hermetically sealed housing to an open housing in fluid communication with the exterior.

A composite circuit protection device includes a transistor, a positive temperature coefficient (PTC) component, a first lead pin, a second lead pin and a third lead pin. The transistor includes a drain electrode, a gate electrode and a source electrode. The PTC component includes a first electrode, a second electrode, and a PTC matrix disposed between the first electrode and the second electrode. The second electrode is in contact with the gate electrode of the transistor. The first lead pin is bonded to the drain electrode of the transistor. The second lead pin is bonded to one of the first electrode and the second electrode of the PTC component. The third lead pin is bonded to the source electrode of the transistor.

The present disclosure provides a semiconductor device that includes a housing having an internal space, at least one semiconductor chip arranged inside the housing, and a separator arranged inside the housing and configured to separate the internal space of the housing into a first chamber and a second chamber. The at least one semiconductor chip is arranged within the first chamber. The separator includes a deformable portion that is configured to deform when a pressure difference between the first and second chambers exceeds a threshold differential pressure or when a temperature at the deformable portion exceeds a threshold temperature, so as to transform the first chamber from a hermetically sealed chamber to an open chamber in fluid communication with the second chamber.

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.