A package structure includes a protection structure, a circuit board, and a chip. The circuit board includes a first cabling layer, a dielectric layer, and a second cabling layer that are laminated. The protection structure is disposed inside the dielectric layer. The protection structure is configured to electrically connect the first cabling layer to the second cabling layer, and the chip is electrically connected to the first cabling layer or the second cabling layer. When the chip is short-circuited, the protection structure blows first.

An integrated circuit (IC) chip having fault protection features. The IC chip in an embodiment may include a lead frame having a first portion adapted to accommodate an IC bare die and a second portion separated from first portion and adapted to be configured as an electrically conductive lead pad. The electrically conductive connector includes a lead fuse section having a reduced size in comparison with a remainder of the second portion.

An integrated circuit (IC) chip having fault protection features. The IC chip in an embodiment may include a lead frame having a first portion adapted to accommodate an IC bare die and a second portion separated from first portion and adapted to be coupled to the IC bare die by an electrically conductive connector. The electrically conductive connector includes a connector bridging portion having a reduced size in comparison with a remainder of the electrically conductive connector and having an elevated portion that is protruding relative to the remainder of the electrically conductive connector.

An upper semiconductor build has an upper build dielectric; at least two upper build electrical signal contact bonding pads; at least one upper build dummy contact bonding pad; an upper build ground network electrically coupled to the at least two upper build electrical signal contact bonding pads; and an upper build anti-fuse dielectric between the upper build ground network and the upper build dummy contact bonding pad. A lower semiconductor build has a lower build dielectric; at least two lower build electrical signal contact bonding pads; at least one lower build dummy contact bonding pad; a lower build ground network; and a lower build anti-fuse dielectric between the lower build ground network and the lower build dummy contact bonding pad. The two builds are hybrid bonded to each other. When excess charge builds up, the anti-fuse dielectrics are blown and conduct the excess charge to ground.

An electronic module is provided, which comprises a plurality of first field effect transistors (FETs), a plurality of second FETs paired with the first FETs, a controller connected to gate nodes of the first and second FETs, and a plurality of spring assemblies disposed between the paired first and second FETs. Each spring assembly has two ends comprises a disc spring that is clamped and at least one conductive path that connects both ends of the spring assembly. One end of the spring assembly is connected to a press-buffer that contacts at least one first FET, while the other end is connected to another press-buffer that contacts at least one second FET.

A layered body contains: a first resin layer; a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which the first resin layer comprises a storage portion, and the first conductive layer is disposed within the storage portion of the first resin layer. A conductive layered body contains: a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which an adhesive layer is provided between the first conductive layer and the insulating layer, and between the insulating layer and the second conductive layer, respectively.

A layered body contains: a first resin layer; a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which the first resin layer comprises a storage portion, and the first conductive layer is disposed within the storage portion of the first resin layer. A conductive layered body contains: a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which an adhesive layer is provided between the first conductive layer and the insulating layer, and between the insulating layer and the second conductive layer, respectively.

An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

A device which enables protection against an abruptly rising pulse such as an electromagnetic pulse in a compact size at a device level and a semiconductor package in which the device is mounted are provided. The semiconductor package (1, 2, 3) includes a substrate (12, 60, 70), an IC chip (21) arranged on the substrate (12, 60, 70), a plurality of connection parts (30) configured to connect the IC chip (21) to the outside, a plurality of bonding wires (40) configured to connect the IC chip (21) and corresponding ones of the plurality of connection parts (30), and a mechanism configured to bypass surge current applied to any of the plurality of connection parts (30) from the connection parts (30) to a ground potential via a path different from the plurality of bonding wires (40).