A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

A chip includes a chip substrate having a first thickness and including a back surface. The back surface includes an etched portion with an etching depth that is less than the first thickness. The chip further includes a first thin film including a dielectric material and located on the back surface. The chip further includes a second thin film including a barrier layer material and located on the first thin film. The chip further includes a third thin film including a metal material, embedded in the chip substrate, and located on the second thin film. The chip further includes a coverage layer including nitride or carbon nitride and located on the first thin film, the second thin film, and the third thin film.

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

According to some example embodiments, an integrated circuit includes a first inter-wiring insulating film on a substrate, a first and second wiring patterns spaced apart from each other on the first inter-wiring insulating film, a first etch stop layer on the first inter-wiring insulating film, the first and second wiring patterns, and a second inter-wiring insulating film on the first etch stop layer. Each of the first and second wiring patterns includes a first lower pattern in the first inter-wiring insulating film, and a first upper pattern on an upper surface of the first inter-wiring insulating film. The first etch stop layer extends along profiles of the upper surface of the first inter-wiring insulating film, and a side face and an upper surface of the first upper pattern. The second inter-wiring insulating film defines a first void between the first wiring pattern and the second wiring pattern.

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of dielectric materials interleaved with levels of conductive materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending in a direction from the first conductive level to the second conductive level, the second conductive level including a side wall; a conductive contact extending in the direction from the first conductive level to the second conductive level and contacting the second conductive level; a first dielectric material between the first conductive level and the conductive contact, the first dielectric material having a first dielectric constant; and a second dielectric material between the first dielectric material and the conductive contact, the second dielectric material having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant.