An integrated circuit device includes a substrate, a first transition metal dichalcogenide layer over the substrate, a dielectric layer over the first transition metal dichalcogenide layer, a first gate electrode, and a first source contact and a first drain contact. The first transition metal dichalcogenide layer has a surface roughness greater than 0.5 nm and less than 1 nm. The first gate electrode is over the dielectric layer and a first portion of the first transition metal dichalcogenide layer. The first source contact and the first drain contact are respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer. The first portion of the first transition metal dichalcogenide layer is between the second and third portions of the first transition metal dichalcogenide layer.

A method includes: oxidizing a target N.sup.+-type gallium oxide substrate to obtain a first N.sup.-type gallium oxide drift layer formed on an upper surface of the target N.sup.+-type gallium oxide substrate and a second N.sup.-type gallium oxide drift layer formed on a lower surface of the target N.sup.+-type gallium oxide substrate; preparing a first anode electrode on an upper surface of the first N.sup.-type gallium oxide drift layer and a second anode electrode on a lower surface of the second N.sup.-type gallium oxide drift layer; cutting the target N.sup.+-type gallium oxide substrate, to obtain a first N.sup.+-type gallium oxide substrate and a second N.sup.+-type gallium oxide substrate; and preparing a first cathode electrode on a lower surface of the first N.sup.+-type gallium oxide substrate and a second cathode electrode on an upper surface of the second N.sup.+-type gallium oxide substrate, to obtain two Schottky diodes.

Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.

Methods of depositing transition metal dichalcogenide (TMDC) films are described. The TMDC films can be used in electronic devices as, for example, a channel material in both back-end-of-line (BEOL) and front-end-of line (FEOL) applications depending on the TMDC growth temperature.

In a first step S101, a first region in which a polarity inversion layer is formed, and a second region in which the polarity inversion layer is not formed are provided on a substrate. Next, in a second step S102, a first nitride semiconductor is epitaxially grown on the substrate having the first region and the second region along the c-axis direction such that a first semiconductor layer is formed. Next, in a third step S103, a second nitride semiconductor is epitaxially grown on the first semiconductor layer along the c-axis direction such that a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor has different polarization, electron affinity, and band-gap energy from the first nitride semiconductor. The second semiconductor layer forms a heterojunction with the first semiconductor layer. The interface therebetween has a polarization charge, which is positive or negative depending on polarity.

An integrated circuit device includes a transistor, a conductive contact plug, a first interconnect structure, and a conductive structure. The transistor includes a gate structure and source/drain regions at opposite sides of the gate structure. The conductive contact plug is electrically coupled to one of the gate structure and the source/drain regions. The first interconnect structure is disposed over the conductive contact plug. The conductive structure is disposed electrically coupled to the conductive contact plug by the first interconnect structure. The conductive structure includes a fill metal and a transition metal dichalcogenide liner cupping an underside of the fill metal. A bottommost position of the transition metal dichalcogenide liner is lower than a bottommost position of the fill metal.