Provided herein are methods of depositing molybdenum (Mo) films. The methods involve depositing a thin layer of a molybdenum (Mo)-containing film such a molybdenum oxide, a molybdenum nitride, or a molybdenum oxynitride. The Mo-containing film is then converted to an elemental Mo film. A bulk Mo film may then be deposited on the elemental Mo film. In some embodiments, the process is performed at relatively low temperatures.

The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer comprises tantalum, and the assisting blocking layer comprises copper manganese alloy.

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiO.sub.x) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

A method for fabricating an interconnect structure is disclosed. A substrate with a first dielectric layer is provided. A first conductor is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer to expose the top surface of the first conductor. An annealing process is performed on the top surface of the first conductor. The annealing process includes the conditions of a temperature of 400-450 C., duration less than 5 minutes, and gaseous atmosphere comprising hydrogen and nitrogen.

The present disclosure is directed to embodiments of a conductive structure on a conductive barrier layer that separates the conductive structure from a conductive layer on which the conductive barrier layer is present. A gap or crevice extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

A semiconductor device according to the present embodiment includes a wiring layer including a plurality of wires. The wires include first wires and second wires. Each of the first wires has a first width in a direction substantially parallel to the wiring layer. The second wires are arranged at wider intervals than intervals of the first wires. Each of the second wires includes a first wiring member having a second width larger than the first width, and a second wiring member provided on the first wiring member and having a third width larger than the second width.

An embodiment inverter circuit includes a first-conductivity-type semiconductor layer disposed over an interlayer dielectric layer, a gate electrode disposed over the first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer disposed over the gate electrode, a first gate dielectric layer disposed between the first-conductivity-type semiconductor layer and the gate electrode, a second gate dielectric layer disposed between the gate electrode and the second-conductivity-type semiconductor layer, a first source electrode that is in contact with the first-conductivity-type semiconductor layer, a second source electrode that is in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode that is in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type layer and the second-conductivity-type layer includes a metal-oxide semiconductor and/or a multi-layer structure formed in a BEOL process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.

Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.

A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.