The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of through-substrate vias (TSVs), a plurality of insulating segments, and a plurality of liners. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of TSVs penetrate through the substrate. Each of the insulating segments includes an embedded portion disposed in the TSV, and an extension portion disposed over the embedded portion and the first surface. The liner is disposed on a side surface of the TSV and between the side surface and the embedded portion of the insulating segment. The plurality of insulating segments and the plurality of liners are exposed by the second surface of the substrate.

Memory devices, such as three-dimensional cross-point memory devices, and methods of manufacturing such devices are addressed. Multiple methods of manufacturing such memory devices are described to provide improved protection of replacement gate structures, such as word lines and word line liners. These include multiple processing flows which forming one or more additional barrier structures between structures subject to at least partial removal during the processing flow; wherein some portion of the additional barrier structure(s) will remain at the end of manufacturing.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of through-substrate vias (TSVs), a plurality of insulating segments, and a plurality of liners. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of TSVs penetrate through the substrate. Each of the insulating segments includes an embedded portion disposed in the TSV, and an extension portion disposed over the embedded portion and the first surface. The liner is disposed on a side surface of the TSV and between the side surface and the embedded portion of the insulating segment. The plurality of insulating segments and the plurality of liners are exposed by the second surface of the substrate.

Memory devices, such as three-dimensional cross-point memory devices, and methods of manufacturing such devices are addressed. Multiple methods of manufacturing such memory devices are described to provide improved protection of replacement gate structures, such as word lines and in some examples, word line liners. These include processing flows which form one or more additional barrier structures between structures subject to at least partial removal during the processing flow; wherein some portion of the additional barrier structure(s) will remain at the end of manufacturing.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

A film forming method includes: a preparation process of preparing a substrate having a surface from which a first film without containing silicon and a second film are exposed; a first film formation process of forming a self-assembled monolayer, which has a fluorine-containing functional group and inhibits formation of a third film containing silicon, on the first film; a second film formation process of forming the third film on the second film; a modification process of decomposing the self-assembled monolayer by plasma using a gas containing hydrogen and nitrogen while maintaining a temperature of the substrate to be 70 degrees C. or lower, so that a side portion of the third film, which is formed in a vicinity of the self-assembled monolayer, is modified into ammonium fluorosilicate by active species contained in the decomposed self-assembled monolayer; and a removal process of removing the ammonium fluorosilicate.

A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.

An interconnection structure includes a first interconnection layer and a second interconnection layer. The first interconnection layer includes a conductive feature extending through a first dielectric layer. The second interconnection layer includes a metal contact and at least one conductive structure extending through a second dielectric layer formed over the first interconnection layer. The metal contact is configured to overlay and interconnect with the conductive feature. A portion of the conductive feature closest to the conductive structure is recessed with a depth a from a top surface of the conductive feature.