Provided are a gate contact structure and a method of manufacturing the gate contact structure. The gate contact structure includes a gate electrode, an etch stop layer on the gate electrode, a capping layer on the etch stop layer, the etch stop layer and the capping layer defining a contact hole penetrating therethrough, the contact hole including a first portion and a second portion, the first portion being in the etch stop layer and exposing the gate electrode, and the second portion being in the capping layer and in communication with the first portion, a liner along a side of the contact hole, and a gate contact plug being within the liner, wherein the etch stop layer, the gate electrode, and the liner define an air gap adjacent to the first portion of the contact hole.

The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

Provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. An exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.

Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

A semiconductor device includes a plurality of metallization layers vertically disposed with respect to and electrically couple to a plurality of transistors. Each of the plurality of metallization layers includes a metal line and a metal via. Each of the metal lines and the metal vias are coupled to a barrier layer. The metal lines and the metal vias each essentially consist of a first material comprising copper (Cu), silver (Ag), and carbon (C). The barrier layer essentially consists of a second material including zirconium nitride (ZrN).

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.

A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.

Embodiments of the present disclosure include an interconnect structure having a via contact coupled to a middle of line (MOL) contact, a bottom of the via contact being free of a tantalum liner. A metal line is connected to the via contact, an interface between a top of the via contact and the metal line being free of the tantalum liner, the via contact and the metal line comprising copper, the via contact and the metal line being encapsulated with a cobalt liner.

A connection structure for an integrated circuit includes: a 1.sup.st layer including a 1.sup.st metal line; a 2.sup.nd layer, above the 1.sup.st layer, including a 1.sup.st via; and a 3.sup.rd layer, above the 2.sup.nd layer, including a 2.sup.nd metal line connected to the 1.sup.st metal line through the 1.sup.st via, wherein the 1.sup.st via comprises a spacer structure at a side of an upper portion of the 1.sup.st via, the spacer structure comprising an insulation material.