Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and the first die and the second die are in a stacked structure. The stacked structure has the one or more metal layers of the first die disposed between the active layer of the first die and the active layer of the second die.

An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.

A controller applied to a power converter includes a startup and pulse control circuit, a power switch, a startup circuit, and a clamping circuit. The power switch is coupled to a primary side of the power converter and the startup and pulse control circuit, and turned on according to a gate control signal generated by the startup and pulse control circuit. The startup circuit is coupled to the primary side of the power converter, the startup and pulse control circuit and the power switch, and turned on according to a startup signal generated by the startup and pulse control circuit. The clamping circuit is coupled to the startup and pulse control circuit and the power switch, and clamps a current flowing through the startup circuit when the startup circuit is turned on.

A method for forming a semiconductor device structure is provided. The method includes forming a first conductive structure surrounded by a first dielectric layer and forming a second dielectric layer over the first conductive structure and the first dielectric layer. The method also includes forming a via hole in the second dielectric layer, and the via hole exposes the first conductive structure. The method further includes partially removing the first conductive structure through the via hole to form a recess in the first conductive structure. In addition, the method includes forming a second conductive structure filling the recess and the via hole.

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

A method for manufacturing a semiconductor device includes: forming on a substrate, a structure including a plurality of dielectric spacers and a plurality of dielectric portions that are disposed to form a plurality of recesses, such that each of the recesses is formed between a corresponding one of the dielectric spacers and a corresponding one of the dielectric portions; and subjecting the dielectric spacers and the dielectric portions to a plasma treatment process such that the dielectric spacers and the dielectric portions are deformed to form a plurality of capping portions to cap the recesses, respectively, so as to form a plurality of air gaps.

A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.

An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. The width of the lower conductive section on a first boundary between the lower and upper conductive sections in the first direction is greater than the width of the upper conductive section on the first boundary in the first direction and the width of the second conductive pattern on a second boundary between the contact plug and the second conductive pattern in the first direction.