In some embodiments, an interconnect structure includes a first conductive structure disposed in a first dielectric layer, wherein the first conductive structure includes a first barrier layer and a first main conductive layer; a second dielectric layer disposed over the first dielectric layer; and a second conductive structure disposed in the second dielectric layer and over the first conductive structure, wherein the second conductive structure includes: a second barrier layer including a first conductive material selected from Ru or Mo; a second main conductive layer disposed over the second barrier layer and including a second conductive material; and a third conductive material being a dopant doped in the second main conductive layer or being a continuous layer between the second main conductive layer and the second barrier layer, wherein the third conductive material is selected from Mn, Ti, Co, Ru, Al, Zn, In, or combinations thereof.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

An integrated circuit device includes a transistor, a conductive contact plug, a first interconnect structure, and a conductive structure. The transistor includes a gate structure and source/drain regions at opposite sides of the gate structure. The conductive contact plug is electrically coupled to one of the gate structure and the source/drain regions. The first interconnect structure is disposed over the conductive contact plug. The conductive structure is disposed electrically coupled to the conductive contact plug by the first interconnect structure. The conductive structure includes a fill metal and a transition metal dichalcogenide liner cupping an underside of the fill metal. A bottommost position of the transition metal dichalcogenide liner is lower than a bottommost position of the fill metal.

A semiconductor structure includes a base provided with a conductive contact hole, a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole, a semi-metal layer formed on a surface of the metal sulfide layer, a barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole and a conductive contact structure disposed in an accommodation hole delimited by the barrier layer.

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.