Cobalt barrier Chemical Mechanical Planarization (CMP) compositions, systems and methods are provided for the removal of cobalt or a cobalt alloy from the surface of a semiconductor device during its manufacture. The compositions use suitable chemical additives selected from the group consisting of an aliphatic organic carboxylic acid, an aromatic organic carboxylic acid, and combinations thereof; abrasives; an oxidizing agent; and an corrosion inhibitor; to provide tunable cobalt film removal rates, tunable selectivity between cobalt and dielectric or other barrier films, and maintain very low static etching rates on cobalt film.

A method for processing substrates includes subjecting each respective first substrate of a first plurality of substrates to a process that modifies a thickness of an outer layer of the respective first substrate, generating a plurality of groups of process parameter values; generating a plurality of removal profiles, training an artificial neural network by backpropagation using the plurality of groups of process parameter and plurality of removal profiles as training data where the artificial neural network has a plurality of input nodes to receive respective removal values from the removal profile and a plurality of output nodes to output control parameter values, for each respective second substrate of a second plurality of substrates determining a target removal profile, determining respective control parameter values to apply by applying the target removal profile to the input nodes, and subjecting each respective second substrate to the process using the respective control parameter values.

A composition for semiconductor processing includes abrasive particles, and a dishing control additive, comprising a first dishing control additive and a second dishing control additive. The first dishing control additive includes a compound having a betaine group and a salicylic group or a derivative thereof, and the second dishing control additive includes an azole-based compound. The first dishing control additive includes 0.07 parts by weight or more based on 100 parts by weight of the abrasive particles, and the second dishing control additive includes 0.13 parts by weight or less based on 100 parts by weight of the abrasive particles.

The present application discloses a method for manufacturing a metal zero layer, comprising: step 1, etching a zero interlayer film to form a first trench; step 2, performing first Ge ion implantation to form a first Ge layer in the zero interlayer film and achieve first amorphization; step 3, performing second Ge ion implantation to form a second Ge layer in the zero interlayer film and achieve second amorphization, wherein the depth of the second Ge layer is greater than the depth of the first Ge layer, and the second Ge ion implantation is tilt ion implantation; step 4, forming a metal silicide layer on the surface of an amorphous silicon layer in a self-aligned manner; step 5, filling the first trench with a first metal layer; and step 6, performing chemical mechanical polishing to fully remove the first metal layer outside the first trench and achieve planarization.

The present disclosure discloses a method for manufacturing a via, including: forming a first dielectric layer on the surface of an underlying structure; performing patterned etching on the first dielectric layer to form a via opening; forming a first metal layer; performing first-time metal CMP to remove the first metal layer on the outer surface of the via opening, where a top surface of the first metal layer in the via opening is located below a top surface of the first dielectric layer; performing second-time dielectric etch back, to selectively etch the first dielectric layer, lower the top surface of the first dielectric layer as being below the top surface of the first metal layer, and form a metal protrusion of a via; and forming a pattern of an upper metal interconnection layer.

A slurry composition for polishing metal and a method of manufacturing an integrated circuit device, the slurry composition includes a first organic polishing booster including a cationic polymer salt that includes a quaternary ammonium cation; a second organic polishing booster including an organic acid; an oxidizer; a pH adjuster; 0 wt % to about 0.1 wt % of an inorganic abrasive; and water.

A chemical mechanical polishing method includes transferring a substrate onto a chuck supported by a drive shaft when the chuck is located at a first height, raising the chuck to a second height greater than the first height such that a top surface of the substrate is in contact with at least one polishing pad, polishing the substate by the at least one polishing pad, lowering, the chuck to a third height lower than the second height, and transferring the substrate off of the chuck.

Polyurethanes and polishing articles made therefrom including a reaction product of a reactive mixture including a polyol, a diol chain extender, a diisocyanate, a mono-alcohol, and a multifunctional amine are described. The mole ratio of isocyanate groups to hydroxyl groups in the reactive mixture is 0.98 or greater. Such polyurethanes may remain stable even at extended exposure to elevated reactive extrusion temperatures.

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.