A chip structure having an interconnect and a manufacturing method thereof include a buffer layer formed between an upper metal structure and a passivation layer under the upper metal structure so as to prevent fractures, such as cracks, from occurring in the passivation layer due to difference of stress between the upper metal structure and the passivation layer.

A method of manufacturing a semiconductor device includes performing chemical mechanical polishing on a surface using a polishing slurry including abrasives, and first cleaning by supplying a cleaning slurry including soft particles and a dispersion medium to remove the abrasives from a polished surface on which the chemical mechanical polishing is performed he soft particles having a lower hardness than the polished surface, wherein a zeta potential of one of the soft particles and the abrasives at a pH of the cleaning slurry is greater than 0, and a zeta potential of the other of the soft particles and the abrasives at the pH of the cleaning slurry is less than 0.

In an embodiment, a polishing slurry comprises polishing particles, an oxidizer, and a zwitterionic compound. A method for manufacturing a display device using a polishing slurry according to an embodiment includes preparing a substrate, forming a transistor on the substrate, forming an insulating layer on the transistor, patterning the insulating layer to form a trench, depositing metal in the trench on the insulating layer to form a first electrode formation layer, polishing the first electrode formation layer using a polishing slurry to form a first electrode, forming a light emitting layer on the first electrode, and forming a second electrode on the light emitting layer, wherein the first electrode is electrically connected to the transistor, and the polishing slurry includes polishing particles, an oxidizer, and a zwitterionic compound.

Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO.sub.2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.

A substrate processing device includes a platen, a polishing pad disposed on the platen, a first rotating body, a second rotating body spaced apart from the first rotating body, a caterpillar module disposed on a portion of the polishing pad and engaged with the first rotating body and the second rotating body, and a temperature controller thermally connected to the caterpillar module.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A field plate electrode configured from a first conductive film is formed in a trench. The field plate electrode is recessed. A first insulation film in the trench is recessed. A gate insulation film is formed in the trench and, simultaneously, a second insulation film is formed so as to cover the field plate electrode. A gate electrode configured from a second conductive film is formed in the trench. A portion of the gate electrode covering a drawer portion, which is a part of the field plate electrode via the second insulation film, is selectively removed.

During polishing of a backside conductive layer, a sensor of an in-situ eddy current monitoring system is repeatedly swept across the substrate so that each respective sweep of the sensor generates a respective signal trace that includes a sequence of signal values. For each respective signal trace, the sequence of signal values is converted to a corresponding thickness trace that includes sequence of thickness values for different locations on the substrate, thus generating a sequence of thickness traces. For each respective thickness trace in the sequence of thickness traces, a plurality of minima in the respective thickness trace are identified. A sequence of layer thickness values over time is calculated based on the plurality of minima from the respective traces in the sequence of thickness traces. Conductive vias extend through the semiconductor wafer of the substrate to electrically connect the backside conductive layer to a front-side conductive layer.

Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.