A manufacturing method of a semiconductor structure including following steps is provided. A patterned photoresist layer is formed on a substrate by a lithography process. The patterned photoresist layer includes a first opening and a second opening. The first opening includes a first inclined sidewall. An etching process is performed on the substrate by using the patterned photoresist layer as a mask to form a third opening corresponding to the first opening and a fourth opening corresponding to the second opening in the substrate. The third opening includes a second inclined sidewall. A conductive layer is formed on the substrate. The conductive layer fills the third opening and the fourth opening. A portion of the conductive layer is removed by using the conductive layer located in the third opening as a stop layer to form a mark in the third opening and a TSV in the fourth opening.

Synthesis of guanidinium-based polymers is disclosed. Chemical Mechanical Planarization (CMP) slurries comprise abrasives; activator; oxidizing agent; additive comprising guanidinium-based polymers; and water. The use of the synthesized guanidinium-based polymers in the CMP slurries reduces dishing and erosion in highly selective tungsten slurries.

Embodiments of the present disclosure relate to a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure relate to an in-situ defect data analyzer to identify CMP induced defects during polishing processing and cleaning processing performed in the CMP tool. In some embodiments, the CMP tool includes an AI (artificial intelligence)-assisted defect database. The defect database may be used to identify and classify CMP related defects, such as scratch, fall-on slurry residuals, during polishing or cleaning process. As a result, defect warning cycle time for a CMP process is improved significantly.

A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.

A dispersant for chemical mechanical polishing that flattens a surface of at least one of an insulating layer and a wiring layer includes a block copolymer (P) having a polymer block A and B. The polymer block A has a structural unit derived from at least one monomer selected from the group consisting of an amide group-containing vinyl monomer and an ester group-containing vinyl monomer, and the polymer block B has a structural unit having an ionic functional group.

The presently disclosed subject matter includes a method and a computer system dedicated for determining semiconductor specimen topography based on grayscale level (GL) imaging output. According to the disclosed approach, the semiconductor specimen surface is scanned from top-view using an examination tool such as a Scanning Electron Microscopy (SEM) to generate a grayscale level (GL) output image of the scanned surface. The GL output images are processed to deduce the corresponding height values of the scanned semiconductor specimen based on graphical features of the GL output images. The height values are then used for validating CMP hotspot predictions, which enhance the accuracy of hotspot detection and increase the reliability of the dummy fill results.

A slurry composition may include an abrasive, a solvent, and polyol. The abrasive may include any one of metal oxide, metal nitride, metal oxynitride, and a combination thereof. The polyol may have about 0.01 mM to about 500 mM of a concentration. Thus, high polishing selectivities may be provided between a BSi layer, a TiN layer and a SiN layer by controlling a polishing rate of the TiN layer.

The present disclosure provides a polishing composition containing: abrasive grains having surfaces modified with a silane coupling agent and having a positive surface potential, and having an average secondary particle size of 45 nm or more and 100 nm or less, and a silanol group density of more than 0.0/nm.sup.2 and 3.0/nm.sup.2 or less; a surfactant which is an alkyl phosphate having 6 to 18 carbon atoms; and an aqueous dispersing medium.

A method for manufacturing an electrical interconnection structure including a step of providing an initial structure including a substrate, an electrically conductive lower element, a cavity formed in the substrate and having an inner wall internally defining an access to the lower element, and an electrically insulating layer; a step of forming an interconnection element in the cavity; and a final polishing step, wherein a portion of the interconnection element and at least one part of the electrically insulating layer are removed simultaneously by chemical-mechanical polishing using a final polishing agent, thereby forming the electrical interconnection structure.

Polishing compositions and methods are provided which enable barrier polishing with improved flatness for patterned substrates comprising copper, tantalum, and TEOS. Provided are polishing compositions comprising: an abrasive with a mean particle size (MPS) of 100 nm to 150 nm; a phosphate surfactant; an electronic conductivity (EC) controller; an organic acid; and a water-soluble polymer, wherein a ratio of a concentration of the abrasive to a concentration of the phosphate surfactant is greater than or equal to 50 and less than or equal to 1040.