A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate.

A method includes controlling a rotational kinetic energy of a rotor assembly of a wafer-platen, wherein a rotational velocity of the wafer-platen is either increased or decreased. The method further includes generating an electrical energy output of the wafer-platen based on decreased rotational kinetic energy of the wafer-platen. The method further includes storing the electrical energy output by the rotator assembly based on the decreased rotational kinetic energy of the wafer-platen.

In one embodiment, a polishing composition can comprise abrasive particles including zirconia, an oxidizing agent including hydroxylamine and water. The polishing composition can have a high copper removal rate of at least 3500 /min, and a polishing selectivity of copper to silicon dioxide(Cu:SiO.sub.2) can be at least 2.5:1. In another embodiment, a combination product can comprise a first polishing composition and a second polishing composition, wherein each of the first polishing composition and the second polishing composition can comprise abrasive particles including zirconia and an oxidizing agent including hydroxylamine, wherein a hydroxylamine weight % ratio of the first polishing composition to the second polishing composition may be at least 5:1.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

The present invention provides a semiconductor device and a method of fabricating the same, which includes: providing a semiconductor substrate having a first patterned region and a second patterned region and performing floating-gate poly-Si deposition on the semiconductor substrate thereby forming a first poly-Si layer, wherein the first patterned region has a higher feature density than the second patterned region; performing ion implantation on the first poly-Si layer and forming an oxide layer over a top surface of the first poly-Si layer; with the oxide layer in the second patterned region being protected, etching the oxide layer in the first patterned region; performing a CMP process on the first poly-Si layer in the first patterned region and on the oxide layer and the first poly-Si layer in the second patterned region; and forming the semiconductor device on the basis of the first poly-Si layer that has undergone the CMP process.

According to some aspects of the present disclosure, a slurry composition for chemical mechanical polishing may include polishing particles including a piezoelectric material, and an oxidizing agent, wherein the piezoelectric material may include a first piezoelectric material and a second piezoelectric material bonded to the first piezoelectric material, and the first piezoelectric material and the second piezoelectric material may have different bandgaps from each other.

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate. In some examples, linear motion may be used for chemically planarizing.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

One or more dielectric inserts are formed in a through-substrate interconnect structure to prevent, minimize, and/or otherwise reduce the amount of dishing that occurs in the top surface of the through-substrate interconnect structure during planarization of the through-substrate interconnect structure. The dielectric insert(s) are formed of a dielectric material having a hardness that is greater than the hardness of the metal material of the through-substrate interconnect structure. The greater hardness enables the dielectric insert(s) to resist material removal during planarization of the through-substrate interconnect structure, which enables a high uniformity in the material removal rates across the top surface of the through-substrate interconnect structure to be achieved. The reduced amount of dishing during planarization of the through-substrate interconnect structure reduces the likelihood of removal of liner material from one or more liners between the sidewalls of the through-substrate interconnect structure and the substrate layer.