A method according to the present disclosure includes receiving a structure that includes a source/drain feature sandwiched between a first channel region and a second channel region, a first dummy gate stack over the first channel region, a first gate spacer extending along a sidewall of the first dummy gate stack, a second dummy gate stack over the second channel region, a second gate spacer extending along a sidewall of the second dummy gate stack, and an interlayer dielectric (ILD) layer over the source/drain feature and disposed between the first gate spacer and the second gate spacer, selectively recessing the ILD layer to form a top recess, after the selectively recessing, performing an ion implantation process to the structure, and after the ion implantation process, forming a capping layer in the top recess.

A method of chemically etching an underlying material includes selectively modifying the underlying material (e.g., a silicon-containing material, like silicon carbide) using lightweight ions (e.g., hydrogen ions, helium ions, etc.) to form a modified region of the underlying material and chemically etching the modified region using a halogen-containing etchant gas (e.g., a fluorine-containing gas, like sulfur hexafluoride). The underlying material is exposed through openings in a resist layer, which may contain carbon and/or a metal, such as a chemically amplified resist or a metal oxide resist. The selective modification step may implant the lightweight ions into the underlying material. Plasma may be used during one or both of the selective modification step and the chemical etching step. Bias power may be applied during the selective modification step and may be higher than bias power applied during the chemical etching step, which may be zero.

An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

A method of forming a semiconductor device includes: forming semiconductor fin structures over a substrate, where each of the semiconductor fin structures includes a layer stack over a semiconductor fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a capping layer over sidewalls and upper surfaces of the semiconductor fin structures; and forming hybrid fins over isolation regions on opposing sides of the semiconductor fin structures, where forming the hybrid fins includes: forming dielectric fins over the isolation regions; and forming dielectric structures over the dielectric fins, which includes: forming an etch stop layer (ESL) over the dielectric fins; doping the ESL with a dopant; and forming a first dielectric material over the doped ESL.

Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the STI is doped with an n-type impurity, in regions of the STI adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the STI region is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the thickness of the doped STI region may range between 10 and 100 nanometers.

Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

A method for modifying dimensions of features in semiconductor devices, including providing a semiconductor device layer stack including a photoresist layer disposed atop a silicon nitride layer, the photoresist layer having an opening formed therein, performing an ion etching process on the layer stack, wherein an ions pass through the opening in the photoresist layer and etch a corresponding opening in the silicon nitride layer, removing the photoresist layer from the silicon nitride layer, performing a first ion implantation process on the silicon nitride layer at a first temperature, performing a second ion implantation process on the silicon nitride layer at a second temperature lower than the first temperature, and performing a wet etch process on the silicon nitride layer, wherein a portion of the silicon nitride layer implanted by the second ion implantation process is preferentially removed from the silicon nitride layer.