Patent classifications
H10P14/2903
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor structure includes a diamond substrate, a SiC intermediate layer, and a device layer that are stacked. The diamond substrate includes a plurality of first grooves on a side close to the SiC intermediate layer, the plurality of first grooves are spaced apart, the SiC intermediate layer includes a plurality of second grooves on a side close to the diamond substrate, the plurality of second grooves are spaced apart, and the plurality of first grooves and the plurality of second grooves are in a one-to-one correspondence and form a plurality of cavities. Adopting the structure including the diamond substrate, the SiC intermediate layer, and the device layer in the present disclosure may reduce defects caused by a lattice mismatch and a thermal mismatch between a substrate and a device, thereby improving overall quality and reliability of a semiconductor structure.
DISPLAY PANEL INCLUDING SUBSTRATE INCLUDING RESIN LAYER HAVING UPPER SURFACE MODIFIED BY A PLASMA TREATMENT
A display panel according to an embodiment includes a substrate, a thin film transistor disposed on the substrate, and a light emitting element electrically connected to the thin film transistor. The substrate includes a first resin layer, a first barrier layer disposed on the first resin layer, a second resin layer including a lower portion disposed on the first barrier layer and an upper portion having a carbon content less than a carbon content of the lower portion, and a second barrier layer disposed on the second resin layer.
Semiconductor Device and Method of Seamless Diamond Surface Preparation and Deposition
A semiconductor device has a substrate with a diamond material. A surface of the substrate is prepared using a first reaction process. The first reaction process can be etching or polishing with oxygen and methane at a gas mixture ratio of about 1:2. The surface of the substrate is exposed to hydrogen plasma prior to the first reaction process. A diamond layer is formed over the surface of the substrate using a second reaction process. The second reaction process can be nucleation or epitaxial growth. The transition from the first reaction process to the second reaction process is seamless. The transition is seamless by nature of the second reaction process continuing from the first reaction process. The diamond layer can be formed over the surface of the substrate using a third reaction process, such as an epitaxial growth. A semiconductor device is formed in the substrate and diamond layer.
Semiconductor structure with diamond heat dissipation and manufacturing method thereof
Embodiments of this application provide a semiconductor structure, an electronic device, and a manufacture method for a semiconductor structure, and relate to the field of heat dissipation technologies for electronic products. An example semiconductor structure includes a semiconductor device, a bonding layer, a substrate, a conducting via, and a metal layer. The semiconductor device is disposed on an upper surface of the substrate by using the bonding layer. The metal layer is disposed on a lower surface of the substrate. The substrate includes a base plate, a groove formed on the base plate, and a diamond accommodated in the groove. The conducting via penetrates the substrate, the bonding layer, and at least a part of the semiconductor device, and is electrically connected to the metal layer. The groove bypasses the conducting via.
SUBSTRATE FOR FORMING SEMICONDUCTOR DEVICE, SEMICONDUCTOR LAMINATED STRUCTURE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SUBSTRATE FOR FORMING SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR LAMINATED STRUCTURE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A substrate (1) for a semiconductor device of the present invention includes a diamond substrate (10) and a silicon carbide layer (20) located on a part or all of one surface (10a) of the diamond substrate (10), wherein the silicon carbide layer (20) has a thickness of 20 nm or less, and wherein a surface (20a) of the silicon carbide layer (20) has an arithmetic mean roughness Ra of 0.5 nm or less.