A structure includes a first substrate, a second substrate, and an interface region. The first substrate includes a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion. The second substrate includes a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The interface region is between the first layer and the second layer and includes at least one electrically conductive polymer material.

Some example embodiments are directed to a semiconductor device including a substrate including a chip region and a peripheral region, a circuit wiring layer on the chip region of the substrate, an interlayer insulating layer on the chip region of the substrate covering the circuit wiring layer, and extending on the peripheral region of the substrate, a chip pad on the interlayer insulating layer on the chip region, and connected to the circuit wiring layer, and a test pad on the interlayer insulating layer on the peripheral region. A thickness of the test pad is less than a thickness of the chip pad in a direction vertical to an upper surface of the substrate.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

An integrated circuit (IC) assembly method is provided. The method includes fabricating a first wafer including a first device with a back end of line (BEOL) and first terminals of first and second types at the BEOL and fabricating a second wafer including a second device for back side power delivery network (BSPDN) processing, second terminals of the first type, first vias and second vias. The first and second wafers are bonded at the BEOL to connect the second terminals of the first type to a subset of the first terminals of the first type, the first vias to remaining first terminals of the first type, and the second vias to the first terminals of the second type. A BSPDN is built onto a backside of the second wafer to include first and second BSPDN terminals connected to the first and second vias, respectively.

A semiconductor die is proposed, wherein the semiconductor die comprises a microelectronic section and a sensor section. The microclectronic section comprises an integrated circuit. The sensor section adjoins an edge of the semiconductor die. A sensor is also proposed, which comprises such a semiconductor die.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

Disclosed is an integrated circuit device. In some aspects, a device includes a first wafer including a first dielectric layer, a first set of bonding pads disposed in the first dielectric layer and a first circuit disposed on the first dielectric layer, and a second wafer including a second dielectric layer, a second set of bonding pads disposed in the second dielectric layer and a second circuit disposed on the second dielectric layer. The device further includes through-vias including at least one power via in the second wafer, and a backside power distribution network (BSPDN) layer disposed on the second wafer. The first set of bonding pads is bonded with the second set of bonding pads.