A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

Disclosed herein is an electronic component that includes: a substrate; a capacitor on the substrate; a first insulating resin layer embedding therein the capacitor; an inductor provided on the first insulating resin layer and connected to the capacitor, the inductor including a conductor pattern; a second insulating resin layer embedding therein the inductor; a third insulating resin layer on the second insulating resin layer; a post conductor having a lower end and an upper end and penetrating the third insulating resin layer such that the lower end of the post conductor is connected to the inductor; and a terminal electrode on the third insulating resin layer and connected to the upper end of the post conductor. In a thickness direction of the substrate, the height of the post conductor is larger than a thickness of a conductor pattern constituting the inductor.

A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

An integrated device comprising a die substrate; a die interconnection portion coupled to the die substrate; and a metallization interconnect coupled to the die interconnection portion. The metallization interconnect comprises an adhesion metal layer, a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer, and a third metal layer coupled to the second metal layer.

A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.

An image pickup unit includes: an image pickup substrate including a first principal surface and a second principal surface, a light receiving circuit being formed on the first principal surface and a through wiring being placed on an inner surface of a via hole including an opening in the second principal surface; a solder resist film placed around the via hole on the second principal surface and in the via hole in a range from a bottom face to a level not reaching the second principal surface; and a bonding terminal which is made of solder, covers a surface of the solder resist film placed in the via hole, and is bonded to the through wiring on an outer edge of the opening in the via hole, the through wiring being not covered with the solder resist film.

A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a <111> grain orientation normal to a horizontal surface of the structure.

A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.

A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.

A copper interconnect structure for an integrated circuit chip is provided for forming a good electrical solder connection with a large-sized metal wire easily. The copper interconnect structure includes a copper surface, a metal barrier layer, and a weldable metal layer. The weldable metal layer is formed with a thickness ranging from 0.03 micrometers to 0.05 micrometers over the metal barrier layer.