An interconnect structure includes a plurality of first pads, a plurality of second pads, and a plurality of conductive lines. The first pads are arranged to form a first column-and-row array, and the second pads are arranged to form a second column-and-row array. The first column-and-row array, the second column-and-row array and the conductive lines are disposed in a same layer. The first pads in adjacent rows in the first column-and-row array are separated from each other by a first vertical distance from a plan view, the second pads in adjacent rows in the second column-and-row array are separated from each other by a second vertical distance from the plan view. A sum of widths of the conductive lines electrically connecting the first pads and the second pads in the same row is less than the first vertical distance and the second vertical distance from the plan view.

Disclosed herein is an electronic component that includes a mounting surface having a terminal formation area and a plurality of terminal electrodes arranged in an array in the terminal formation area. The center point of the terminal formation area is offset with respect to the center point of the mounting surface. Thus, at mounting of the electronic component on a mounting substrate, a solder paste is supplied to a land pattern, and then the mounting is performed such that the center point of a mounting area and the center point of the mounting surface coincide with each other, whereby a predetermined displacement occurs between the planar positions of the land pattern and terminal electrode. This allows a void inside the solder to be released outside without involving a layout change of the land pattern.

A semiconductor device assembly including a first semiconductor die having a first dielectric region and a first bond pad that are disposed on a first side of the first semiconductor die; a second semiconductor die having a second dielectric region and a second bond pad that are disposed on a second side of the second semiconductor die; and a hybrid bonding interface between the first side of the first semiconductor die and the second side of the second semiconductor die, the hybrid bonding interface including a gap free metal-metal bonding region between the first and the second bond pads and a gap free dielectric-dielectric bonding region between the first and the second dielectric regions, wherein the dielectric-dielectric bonding region includes a nitrogen gradient with a concentration that increases with proximity to the metal-metal bonding region.

A copper diffusion-suppressing electrical bond between a first semiconductor wafer or chip or interposer and a second semiconductor wafer or chip or interposer includes a first bond pad metal with a first bond pad metal surface disposed on the first semiconductor wafer or chip or interposer, bonded with a second bond pad metal with a second bond pad metal surface disposed on the second semiconductor wafer or chip or interposer. A copper outdiffusion-suppressing coating such as a titanium, cobalt, nickel/gold, or nickel/palladium/gold layer may be disposed on the first copper bond pad metal surface and/or on the second copper bond pad metal surface. The copper of the bond pad metal may be doped with manganese to form a copper outdiffusion-suppressing surface manganese oxide. The bond pad metal may alternatively be tungsten to prevent copper outdiffusion.

The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.

A bonding apparatus includes a first holder, a second holder, a moving unit, a housing, an interferometer, a first gas supply and a second gas supply. The first holder is configured to attract and hold a first substrate. The second holder is configured to attract and hold a second substrate. The moving unit is configured to move a first one of the first holder and the second holder in a horizontal direction with respect to a second one thereof. The interferometer is configured to radiate light to the first one or an object moved along with the first one to measure a horizontal distance thereto. The first gas supply is configured to supply a clean first gas to an inside of the housing. The second gas supply is configured to supply a second gas to a space between the interferometer and the first one or the object.

A method for sequencing a hybrid bonding process by double linking a source of dies and a target. The method may include selecting a source of dies for bonding, selecting a target on which the dies will be bonded, linking the source to the target, linking the target to the source, forming an integrated bonding product sequence that includes a first linked bonding sequence for the source and a second linked bonding sequence for the target, determining bonding process chamber allocations and process timing for the source and the target based on the integrated bonding product sequence, and bonding a die from the source to the target using the integrated bonding product sequence.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

A method of manufacturing a semiconductor package includes providing a wafer substrate including a first a chip area and an edge area; forming first and second conductive layers on the wafer substrate; forming a photoresist pattern, including openings, on the second conductive layer, wherein the photoresist pattern includes a first photoresist pattern on the chip area and a second photoresist pattern on the edge area; forming conductive patterns within the openings; removing the first photoresist pattern from the photoresist pattern, and portions of the first and second conductive layers overlapping with the first photoresist pattern; removing the second photoresist pattern from the photoresist pattern, and a portion of the second conductive layer overlapping the second photoresist pattern, such that a portion of the first conductive layer on the edge area is exposed; and forming a protective film such that the protective film is on the conductive patterns.