A high voltage semiconductor device isolation structure and a method of manufacturing the same prevent a silicon penetration region from being formed between a first STI region and the side wall of a DTI region so that the breakdown voltage characteristic of a device is prevented from being decreased due to electric field concentration on the penetration region, and a method of manufacturing the same.

A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth, and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level.

An object is to provide a technique that ensures to reduce a parasitic resistance of a semiconductor device while enhancing a breakdown voltage property of a semiconductor device. A portion of a second semiconductor layer exposed from a first semiconductor layer corresponds to a concave portion of a laminated structure and the first semiconductor layer or an adjacent portion of the first semiconductor layer and a second semiconductor layer corresponds to a convex portion of the laminated structure. A first guard ring of a second conductivity type is arranged on side walls of the convex portion, and in the concave portion, a guard ring of the second conductivity type is not arranged, or a second guard ring of the second conductivity type having a thickness thinner than that of the first guard ring is arranged.

In one aspect, a silicon-on-insulator semiconductor device includes: a substrate; a buried dielectric layer disposed on the substrate; a first electrode; a second electrode; and a drift region disposed on the buried dielectric layer. An upper surface of the drift region forms a drop structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side. An upper surface of the second side is higher than a bottom surface of the first side, such that a thickness of the drift region at the second side is greater than that at the first side. The first electrode and the second electrode are configured such that a voltage applied to the second electrode is greater than a voltage applied to the first electrode when a reverse bias voltage is applied to the device.

Provided is a fabrication method of a semiconductor device, the fabrication method including applying a protective film to a front surface of a semiconductor wafer, patterning the protective film, performing backside processing of the semiconductor wafer in a state in which the protective film that is patterned of the front surface is supported by a support stand in a vacuum chamber, and removing the protective film after the backside processing of the semiconductor wafer is performed. The performing the backside processing may include performing ion implantation into a back surface of the semiconductor wafer. The protective film may be polyimide.

The present disclosure relates to a method for manufacturing a semiconductor structure. The method comprises providing a first structure. The first structure comprises a first substrate. The method comprises providing a second structure. The second structure comprises a second substrate and a first device metal layer on and in contact with the second substrate. The second substrate comprises a single crystalline semiconductor material and an implanted hydrogen layer. The method comprises bonding the first structure and the second structure by a bonding layer to form a bonded structure. The method comprises removing a portion of the second substrate from approximately the implanted hydrogen layer to form a first semiconductor layer. The method comprises patterning the first semiconductor layer. The method comprises forming at least one of a second device metal layer and a second conductive metal layer.

A semiconductor device includes: a semiconductor body having a first surface and a second surface; a plurality of semiconductor device elements in the semiconductor body at the first surface; a wiring area over the first surface of the semiconductor body; and an impurity in the semiconductor body. A profile of concentration of the impurity has a penetration depth from the second surface into the semiconductor body along a vertical direction. The profile of concentration has a concentration plateau along a vertical segment ranging from 30% to 70% of the penetration depth, the plateau having a fluctuation of the concentration of less than 20%.

An ion implanter may include an ion source, arranged to generate a continuous ion beam, a DC acceleration system, to accelerate the continuous ion beam, as well as an AC linear accelerator to receive the continuous ion beam and to output a bunched ion beam. The ion implanter may also include an energy spreading electrode assembly, to receive the bunched ion beam and to apply an RF voltage between a plurality of electrodes of the energy spreading electrode assembly, along a local direction of propagation of the bunched ion beam.

A semiconductor device includes a chip formed by a wide bandgap semiconductor and having a principal surface on which a semiconductor region of a first conductivity type is formed, a base impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region, a first impurity region formed in a surface layer portion of the base impurity region, and a second impurity region of a conductivity type opposite to that of the first impurity region formed in the surface layer portion of the base impurity region, the second impurity region being adjacent to the first impurity region in a first direction, wherein the second impurity region is formed in a band shape extending in a second direction orthogonal to the first direction, and includes a projection portion selectively protruding toward the first impurity region in the first direction.

The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.