A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer has a higher germanium concentration than the second semiconductor layer; forming a semiconductor cap over the second semiconductor layer; forming a first bonding layer over the semiconductor cap; bonding the first boding layer to a second bonding layer over a carrier substrate to form a bonded structure; and performing a wafer splitting process to split the first semiconductor layer into a first portion and a second portion separated from each other, such that the first portion of the first semiconductor layer and the substrate are removed from the bonded structure.

A nitride-based semiconductor device includes first and second nitride-based semiconductor layers, first electrodes, doped nitride-based semiconductor layers, a second electrode, and gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion surrounding the active portion. The first electrodes are disposed over the second nitride-based semiconductor layer. The first electrodes, doped nitride-based semiconductor layers, the gate electrode, and the second electrode are disposed over the second nitride-based semiconductor layer. Each of the doped nitride-based semiconductor layers has a side surface facing away from the second electrode and spaced apart from the interface.

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

A diode device includes a semiconductor substrate, isolation structures, and metal silicide layers. The semiconductor substrate includes a well region and first to third doped regions in the well region. The first and second doped regions have opposite conductivity types, and a conductivity type of the well region is the same as the conductivity type of the second doped region. The third doped region is between the first and second doped regions. A conductivity type of the third doped region is the same as the conductivity type of the first doped region, and a dopant concentration of the third doped region is greater than a dopant concentration of the first doped region. The isolation structures are in the semiconductor substrate and spacing the first to third doped regions apart from each other. The metal silicide layers are respectively over the first and second doped regions.

An impurity region of P-type that the field effect transistor of the nitride semiconductor device includes has a peak position at which concentration of P-type impurities reaches a maximum at a position located away from an interface with a gate insulating film. The impurity region has an inflection point at which concentration of the P-type impurities changes from increase to decrease toward the interface or a rate of decrease in the concentration of the P-type impurities increases toward the interface at a position located between the interface and the peak position.

A trench MOSFET with reduced gate capacitances, and a method of making the same. The reduction of the gate capacitances is achieved with asymmetric dielectric gate oxide on the sidewalls and bottom of the trench, with the gate oxide being thinner on the channel side and thicker on the opposite side and bottom. Silicon is implanted into a partial MOSFET structure, resulting in silicon-rich silicon carbide. A trench is asymmetrically etched into the implanted silicon, leaving a thicker layer of the implanted silicon on the second sidewall and bottom of the trench than on the first sidewall. A layer of silicon dioxide is grown over the first and second sidewalls and bottom of the trench, and the growing oxide converts the silicon-rich silicon carbide into additional silicon dioxide, resulting in a thicker layer of silicon dioxide at the second sidewall and bottom of the trench than at the first sidewall.

Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 m or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 m or more in a direction from the local maximum of the hydrogen peak toward the upper surface.

The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

A power element and a manufacturing method for the power element are provided. The power element that is manufactured is a trench-type metal oxide semiconductor field-effect transistor having a junction field-effect transistor region. The power element includes a substrate, a drift diffusion layer, a body layer, a plurality of gate trenches, polycrystalline silicon, a plurality of first doped regions, a plurality of second doped regions, a plurality of protective doped regions, a plurality of dielectric layers, and a metal conductive layer.