There is provided a memory device including a first chip including a first normal region, the first region including a plurality of first normal connectors on a first surface and configured to be provided with signals used during an operation of memory cells, and a first test region including a plurality of first connectors on the first surface and electrically connected to each other, and a second chip. The second chip includes a second normal region including a plurality of second normal connectors, and configured to provide signals used during the operation of the memory cells to the first normal connectors, and a second test region including a plurality of first and second test connectors on the second surface so as not to overlap the plurality of first connectors in the first direction, and configured to not be provided with signals used during the operation of the memory cells.

A substrate bonding device including: a bonding chamber including (i) a loading region in which a lower substrate is loaded, (ii) a bonding region in which an upper substrate is bonded to the lower substrate, and (iii) an unloading region spaced from the loading region and unloading the lower substrate to which the upper substrate is bonded in an internal space; a plurality lower chucks configured to support the lower substrate, each lower chuck moveable to be sequentially disposed in the loading region, the bonding region, and the unloading region; and an upper chuck configured to support the upper substrate to face the lower substrate in the bonding region.

A method includes bonding a first wafer to a second wafer; after bonding the first wafer to the second wafer, bonding a third wafer to the first wafer; conducting a process control monitor on the first and second wafers via a first electrical pathway that traverses an interface between the first and second wafers; determining whether a charge present at the interface between the first and second wafers.

A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

A bonding apparatus includes a first holder, a second holder, a moving unit, a housing, an interferometer, a first gas supply and a second gas supply. The first holder is configured to attract and hold a first substrate. The second holder is configured to attract and hold a second substrate. The moving unit is configured to move a first one of the first holder and the second holder in a horizontal direction with respect to a second one thereof. The interferometer is configured to radiate light to the first one or an object moved along with the first one to measure a horizontal distance thereto. The first gas supply is configured to supply a clean first gas to an inside of the housing. The second gas supply is configured to supply a second gas to a space between the interferometer and the first one or the object.

A method for sequencing a hybrid bonding process by double linking a source of dies and a target. The method may include selecting a source of dies for bonding, selecting a target on which the dies will be bonded, linking the source to the target, linking the target to the source, forming an integrated bonding product sequence that includes a first linked bonding sequence for the source and a second linked bonding sequence for the target, determining bonding process chamber allocations and process timing for the source and the target based on the integrated bonding product sequence, and bonding a die from the source to the target using the integrated bonding product sequence.

A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a first wafer structure and at least one die stack layer stacked on a second side of the first wafer structure. The die stack has first test pad and second test pad, which can be used to test and screen the die in the die stack and the die stack, contributing to increased yield of the semiconductor device. Additionally, metal pad may be formed on a first side of the first wafer structure before the die stack is stacked on the first wafer structure, avoiding warpage or other distortion possibly otherwise caused by high-temperature treatment if they are formed after the die stack is stacked. This facilitates stacking of more dies and/or wafers together. The semiconductor device is obtainable according to the method.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Bonded die structures and methods of fabricating bonded die structures with improved stress distribution. A bonded die structure may include a second die bonded to a first die. The sizes, shapes and/or relative position of the first die with respect to the second die may be configured to minimize stress concentrations in the bonded die structure. In some embodiments, a length dimension of a corner region of the second die may be less than a length dimension of the adjacent corner region of the first die, which may aid in redistributing stress away from the corner of the first die. An offset distance between the corner of the second die and the corner of the first die may also be controlled to minimize stress applied to the corner of the first die along a vertical direction. Accordingly, crack formation may be reduced, and device performance and yields may be improved.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.