A display device includes a display panel including a display area and a pad area. The display panel includes a base substrate, a pixel, a pad group, an alignment mark, and a protective layer. The pad group includes a plurality of pads arranged in a first direction. The alignment mark is spaced apart from the pad group in the first direction. The protective layer covers the pads and the alignment mark and a plurality of openings respectively exposing upper surfaces of the pads is defined in the protective layer. Each of the pads includes at least one pad pattern, and the alignment mark is disposed in a same layer as a pad pattern spaced farthest from the base substrate among the at least one pad pattern.

A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.

Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.

A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

A semiconductor chip including a plurality of first pads, a plurality of second pads, a plurality of first bumps, and a plurality of second bumps is provided. The first pads and the second pads are arranged along a direction of a long side of an active surface of the semiconductor chip. The first bumps are disposed on the first pads, and configured for a chip probe test. The second bumps are disposed on the second pads, and not for the chip probe test. A size of the first bump is larger than a size of the second bump.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first wiring structure including a first wiring pattern and a first wiring insulating film, a second semiconductor chip including a second semiconductor substrate and a second wiring structure including a second wiring pattern and a second wiring insulating film, a first bonding pad on the first wiring structure, a first passivation layer surrounding a side surface of the first bonding pad, a second bonding pad electrically connected to the first bonding pad, a second passivation layer surrounding a side surface of the second bonding pad, a first alignment inspection structure horizontally apart from the first wiring pattern and penetrating the first passivation layer, and a second alignment inspection structure vertically penetrating the second semiconductor substrate, the second wiring insulating film, and the second passivation layer.

Some embodiments relate to an integrated device, including: a first interconnect structure on a first substrate; a first central bond pad coupled to the first interconnect structure; a first peripheral bond pad on a first side of the first central bond pad separated by a first distance; a second peripheral bond pad on a second side of the first central bond pad and separated by a second distance substantially equal to the first distance; a second interconnect structure on a second substrate; a first overlying bond pad coupled to the second interconnect structure and bonded to the first central bond pad; and a plurality of exposed bond pads respectively coupled to the first central bond pad, the first peripheral bond pad, the second peripheral bond pad, and the first overlying bond pad, wherein the plurality of exposed bond pads extend past outer sidewalls of the second substrate.

Provided is a semiconductor device, including: a protective film provided above a front surface of a semiconductor substrate; and a front surface electrode provided above the front surface of the semiconductor substrate; where the front surface electrode includes: a plurality of bonding regions exposed through a plurality of opening portions provided in the protective film; and a plurality of testing regions for testing, and where in a top view of the semiconductor substrate, an area of each testing region is smaller than an area of each bonding region. Furthermore, provided is a semiconductor module including a semiconductor device.

A display panel, a circuit board and a display device are provided, belonging to the field of displays. The display panel has a display region and a binding region which is on at least one side of the display region, and the display panel includes: a substrate; a plurality of signal pins on the substrate and in the binding region, the signal pins being arranged at intervals in a first direction and being connected to the circuit board; and at least one non-signal pin on the substrate and between two adjacent signal pins.

According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.