A semiconductor package including: a first semiconductor chip; and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes: a first substrate, a first semiconductor device provided on a first surface of the first substrate, a first interconnection layer on the first surface of the first substrate, an insulating layer covering a second surface of the first substrate that is opposite to the first surface of the first substrate, a first via and a second via penetrating the first substrate and the insulating layer in a first direction that is perpendicular to the first surface of the first substrate, and a connection pattern on a surface of the insulating layer and connected to the first via and the second via, wherein a surface of the first via is coplanar with the surface of the insulating layer.

Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (die) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, a second semiconductor die, a first thermal interface material (TIM) film, a second TIM film, and a heat-dissipating lid. The redistribution layer is attached to the substrate. The first semiconductor die and the second semiconductor die are disposed over the redistribution layer. The first TIM film is formed over the first semiconductor die. The second TIM film is formed over the second semiconductor die. The heat-dissipating lid is attached to the substrate. The heat-dissipating lid has first regions with a first cavity depth and a second region with a second cavity depth. The second cavity depth is greater than the first cavity depth. The second TIM film is disposed in the second region of the heat-dissipating lid.

A display apparatus includes: a circuit board including a driving circuit; and a pixel array disposed on the circuit board and including pixels, each of the pixels having a plurality of sub-pixels. The pixel array includes: a semiconductor stack, a conductive partition structure and wavelength conversion portions. The semiconductor stack includes LED cells respectively constituting the plurality of sub-pixels. Each of the LED cells includes at least an active layer and a second conductivity-type semiconductor layer. The conductive partition structure is provided between sub-pixel spaces, respectively overlaps the LED cells on the semiconductor stack, and is provided as a first electrode. The wavelength conversion portions are respectively disposed on the sub-pixel spaces.

A bonding structure of a semiconductor package device that physically and electrically connects between a semiconductor chip and a package substrate or between a package substrate and a board, the bonding structure includes a solder; a main pad that faces the solder; and an electrically conductive support structure that is connected between the solder and the main pad, the electrically conductive support structure including a sub pad bonded to the solder, the sub pad being spaced apart from the main pad and facing the main pad, and at least one leg extending from the sub pad to the main pad.

A semiconductor device includes a substrate having a front surface and a rear surface. The device includes a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns disposed adjacent to the first gate electrode. The device includes a front surface dummy stack structure disposed on the first transistor and electrically floated, the front surface dummy stack structure extending from a lower end to an upper end, the lower end being spaced apart from the first transistor. The front surface dummy stack structure includes alternately stacked front surface dummy vias front surface dummy wires that overlap the first gate electrode such that heat generated in the first transistor is transferred to the upper end of the front surface dummy stack structure through the plurality of front surface dummy vias and the plurality of front surface dummy wires.

A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

Semiconductor devices and methods of forming the same include a device layer, a back-end-of-line (BEOL) layer on the device layer, a combined bonding layer, and a handler wafer. A heat-conducting channel is partially embedded in the combined bonding layer and partially embedded in the handler wafer.

A display panel, a display screen, and a manufacturing method of a display screen are provided. The display panel includes a light-emitting assembly, a driving assembly, multiple first conductive members, and multiple second conductive members. The light-emitting assembly includes multiple light-emitting units, where each of the multiple light-emitting units includes a first electrode and a second electrode spaced apart from the first electrode, and the first electrode surrounds the second electrode. The driving assembly includes multiple driving units, where one of the multiple driving units is disposed in correspondence with one of the multiple light-emitting units, and different driving units correspond to different light-emitting units. Each of the multiple driving units includes a third electrode and a fourth electrode spaced apart from the third electrode, and the third electrode surrounds the fourth electrode. Each of the multiple first conductive members couples the first electrode with the third electrode.