An electronic package and a manufacturing method thereof are provided. The electronic package includes an electronic component and a shielding layer. The electronic component has an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface and the active surface. The shielding layer is disposed on the electronic component and directly contacts and completely covers the inactive surface and the side surface. The shielding layer is formed directly on the surface of the electronic component, thereby shielding electromagnetic interference, reducing the size of the electronic package, and lowering production costs.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.

A semiconductor structure includes a plurality of first wafers and a through-substrate via (TSV). The plurality of first wafers include a plurality of conductive connection lines. Each of the conductive connection lines is located in the corresponding first wafer. The through-substrate via passes through the plurality of first wafers and a plurality of end portions of the plurality of conductive connection lines. The plurality of end portions are embedded in the through-substrate via.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Provided is a printed circuit board including a substrate structure having a first surface including a chip mounting region on which a semiconductor chip is mounted and a second surface opposite to the first surface, the second surface having a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge and a first corner, a second corner, a third corner, and a fourth corner formed by the first to fourth edges, and pad patterns disposed on the second surface of the substrate structure, wherein the second surface includes a first region including a region corresponding to the chip mounting region and in contact with the first to fourth edges of the second surface, respectively, and second regions adjacent to the first to fourth corners of the second surface, respectively and spaced apart from each other by the first region, wherein the pad patterns include first pad patterns disposed in the first region and surface-treated with a nickel/gold (Ni/Au) layer, and second pad patterns disposed in the second regions and surface-treated with an organic solderability preservative.

A light-emitting device includes a carrier substrate, a flip-chip light-emitting diode (LED) mounted onto the carrier substrate, and an electrode unit disposed between the carrier substrate and the flip-chip LED. The electrode unit includes first and second connecting electrodes that have opposite conductivity. Each of the first and second connecting electrodes includes an intermediate metal layer and a binding layer that are sequentially disposed on the flip-chip LED in such order. The binding layer includes a first portion being adjacent to the carrier substrate and forming an eutectic system with tin, and a second portion located between the first portion and the intermediate metal layer.

A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.