There is provided a vertical device including: a semiconductor substrate which has an upper surface and a lower surface; and a lower electrode which is provided on the entire lower surface of the semiconductor substrate, in which the lower electrode contains copper. The lower electrode may have a lowermost layer which is exposed at a surface that is farthest away from the lower surface of the semiconductor substrate, the lowermost layer may contain copper, a ratio of copper in the lowermost layer may be 50 wt% or more and 90 wt% or less, and a thickness of the lowermost layer may be 0.2 m or more and 0.8 m or less.

A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.

The present invention relates to a power module and a method for manufacturing same, the power module including: a lower ceramic substrate; an upper ceramic substrate which is disposed spaced apart from the upper portion of the lower ceramic substrate, and on the lower surface of which a semiconductor chip is mounted; spacers each having one end bonded to the lower ceramic substrate and the other end bonded to the upper ceramic substrate; first bonding layers each bonding the one end of each spacer to the lower ceramic substrate; and second bonding layers each bonding the other end of each spacer to the upper ceramic substrate. The present invention maintains a constant distance between the lower ceramic substrate and the upper ceramic substrate by having the spacers arranged therebetween, and thus is advantageous in that the semiconductor chip can be protected and heat dissipation efficiency can be increased.

A semiconductor device includes a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate, a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction on the first surface, the first source finger being electrically connected to the source bus bar, and a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar.

A low parasitic inductance power module having staggered, interleaving busbars, including: at least one base extending a long a length direction, the base having at least one current input busbar and at least one current output busbar, the current input busbar and the current out busbar being formed with a plurality of interdigitated contact terminals, respectively; a first unit comprising a first circuit base portion disposed on the base along the width direction, on the first circuit base portion being disposed a plurality of first power devices; and a second unit, whereby when current flows through the units and the individual interdigitated contact terminals, individual inductances produced thereby are cancelled with each other, whereby overall parasitic inductance of the power module is reduced.

A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

A transistor, an inverter, a manufacturing method of an inverter and a memory unit are provided. The transistor including a substrate, a stacked structure, and a gate structure. The stacked structure is disposed on the substrate and includes a drain electrode, a source electrode, a semiconductor layer, a first buffer layer, and a second buffer layer. The gate structure includes a gate electrode and a gate dielectric layer. By forming the doped region in the buffer layer to dispose the channel region contact between the source electrode and the drain electrode, the channel layer having the vertical structure is formed, and thereby the vertical transistor having a novel structure is formed. By stacking two transistors on the substrate and allowing the two transistors to share the gate structure, the inverter can have the three-dimensional structure, and the area of the inverter can be reduced to have a relatively small dimension.

Power semiconductor device packages and methods for manufacturing the same are provided. In one example, a power semiconductor device package may include a housing, a submount, and a conjoined semiconductor die structure on the submount. The conjoined semiconductor die structure may include at least two semiconductor die having a common substrate. The conjoined semiconductor die structure may be cut from a semiconductor wafer and may be packaged based on die viability data indicative of an operability of each respective semiconductor die of the at least two semiconductor die.

A semiconductor circuit, including a plurality of first devices and a plurality of second devices provided on the front surface of the main board, wherein each of the first device and the second device has a plurality of electrodes including a first main electrode and a second main electrode arranged on an upper surface, and the first main electrode and the second main electrode are connected to the front surface of the main board; each of the first devices has a first end side facing the second device; each of the second devices has a second end side facing the first device; a whole region between the first main electrode and the first end side in the first direction is a first region; and a whole region between the second main electrode and the second end side in the first direction is a second region.