A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A system comprises: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power switch including a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch, and control a gate control signal to the gate terminal based on the detected change in current.

A cooling apparatus for a semiconductor arrangement is made by producing a base body with a flat surface, opposing first and second lateral surfaces, and channels extending continuously from the first to the second lateral surface and parallel to the flat surface, with adjacent ones of the channels being each connected via a web. Bilaterally introduced in the base body are contacting grooves and connecting grooves in parallel relation to the flat surface by partially removing the web between the adjacent channels such that the connecting grooves are arranged between the adjacent channels, the channels are arranged between the flat surface and the contacting grooves, and the connecting grooves protrude deeper into the base body than the respective contacting grooves. The channels are closed to form a closed channel structure which is filled with a heat transfer fluid so that the base body is directly contacting the heat transfer fluid.

In one example, an electronic device comprises a substrate comprising a conductive structure and an inner side and an outer side, a first electronic component over the inner side of the substrate and coupled with the conductive structure, a lid over the substrate and the first electronic component and comprising a first hole in the lid, and a thermal interface material between the first electronic component and the lid. The thermal interface material is in the first hole. Other examples and related methods are also disclosed herein.

A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a first electrically conductive spacer coupled to inner surface of the first substrate and to the inner surface of the second substrate.

A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

A semiconductor package includes a semiconductor element, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer. The first insulating layer covers the semiconductor element. The first wiring layer includes a first layer section. The first layer section covers the first insulating layer. The second insulating layer covers the first insulating layer and the first wiring layer. The second wiring layer is electrically connected to the semiconductor element through a second through hole and a third through hole. The second wiring layer includes a second layer section. The second layer section covers the second insulating layer. The second layer section of the second wiring layer has a portion overlying the first layer section of the first wiring layer with the second insulating layer interposed.

A semiconductor device, including a cooling body, a semiconductor unit including a wiring portion electrically connected to a semiconductor chip, and a sealing member sealing the entire semiconductor unit over a cooling surface of the cooling body. The sealing member includes a first portion and a second portion which surrounds the first portion in a plan view. The first portion seals a central portion of a main electrode of the semiconductor chip, and has a first sealing surface opposite the cooling surface of the cooling body. The second portion seals a wiring portion to thereby surround the first portion in the plan view, and has a second sealing surface opposite the cooling surface. A distance in a thickness direction of the semiconductor device from the cooling surface to the first sealing surface, is smaller than a distance in the thickness direction from the cooling surface to the second sealing surface.

An electronic device and a method of manufacturing an electronic device are provided. The electronic device includes a first conductive layer and a first power die. The first conductive layer including a first part and a second part separated from the first part. The first power die is disposed above the first conductive layer and has a first surface. The first power die includes a first terminal exposed from the first surface and a second terminal exposed from the first surface. The first part is electrically connected to the first terminal and the second part is electrically connected to the second terminal.

Disclosed is a bonded structure including an element with a bonding surface, the bonding surface having a dielectric region and a first semiconductor region laterally spaced from the dielectric region. The bonded structure further includes a first die directly bonded to the dielectric region of the element without an intervening adhesive. The bonded structure further includes a second die having a second bonding surface having a second semiconductor region, the second semiconductor region being bonded to the first semiconductor region of the element without an intervening adhesive and without an intervening deposited dielectric material.