A semiconductor device includes: a substrate including a main chip area and a scribe lane area, wherein chip circuits are disposed in the main chip area, and the scribe lane area surrounds the main chip area; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer and in which a plurality of guard rings are embedded; a dielectric layer disposed on the second insulating layer; and a third insulating layer disposed on the dielectric layer, wherein the scribe lane area includes a first area and a second area, wherein the first area is adjacent to the main chip area based on a decreasing point of a thickness of the third insulating layer, wherein the plurality of guard rings includes a first guard ring disposed in the first area and a second guard ring disposed in the second area.

Provided are an SiC-semiconductor device (1) having properties capable of maximizing the device strength when cut from an SiC-semiconductor wafer (11) by SnB, and a method of manufacturing the SiC-semiconductor device.

The SiC-semiconductor device is produced by, after forming scribe lines (L) in the wafer (11) with a scribing tool, dividing the wafer with external-force application along the lines (L). Created in a sidewall surface of the device (1) is a longitudinal stripe (TL) extending continuously to C surface from a predetermined depth in the sidewall surface exclusive of plastically-deformable region of Si surface and vertical-cracking region formed immediately below the plastically deformable region. The stripe (TL) fulfills the condition of being rectilinearly-shaped or the condition where exterior angle formed by intersection of a longitudinal stripe (TL) extending upward from the C (lower) surface with a deflected stripe (KL) resulting from first-time deflection of the stripe (TL) falls within 10.

A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source/drain feature in the recess.

Provided is a method for fabricating a semiconductor device, the method including exposing a first pattern corresponding to a mask pattern to light in a first shot region of a substrate by using a photomask including the mask pattern, the first pattern extends in a first direction, and exposing a second pattern corresponding to the mask pattern to the light in a second shot region disposed adjacent to the first shot region of the substrate by using the photomask, the second pattern extends in a second direction, wherein the first direction crosses the second direction.

An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Provided is a method of manufacturing a silicon carbide semiconductor device that suppresses the crawling up of a bonding material to the side surfaces of a chip, thereby suppressing a decrease in productivity. In the method of manufacturing the silicon carbide semiconductor device, the method includes, preparing a semiconductor wafer, forming semiconductor elements on the semiconductor wafer, forming a trench, which has a bottom having a roundness, on one main surface of the semiconductor wafer, and performing dicing at a position of the trench having the bottom having the roundness thereby separating the semiconductor elements into individual pieces.

In a dividing method of a wafer, first edge parts and second edge parts that are the edges of chips are melted by executing irradiation with a laser beam. Therefore, the edges of the chips can be planarize. In addition, cracks, chipping, and so forth caused in the edges of the chips can be coupled. Therefore, it becomes possible to repair at least part of processing strain of the edges of the chips. As a result, a flexural strength of the chips can be enhanced.