A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Embodiments of the present disclosure generally relate to methods and processes to selectively deposit Si:P layers onto a semiconductor structure. More specifically, embodiments described herein provide for methods for enhancing epitaxial deposition of Si:P layers onto semiconductor structures at lower temperatures. In some embodiments, a method includes positioning a substrate within a processing volume of a processing chamber, introducing a process gas such as a silicon source and a dopant gas to the processing chamber, and forming an epitaxial layer on a surface of the substrate at a processing temperature of about 450 C. or less. The partial pressure of the silicon source is preferably about 10 Torr to about 300 Torr.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.010.sup.14 cm.sup.3 at any position in the plane of the epitaxial layer.

Methods for forming structures that include forming a heteroepitaxial layer on a substrate are disclosed. The presently disclosed methods comprise epitaxially forming a buffer layer on the substrate. The substrate has a substrate composition. The buffer layer has a buffer layer composition. The buffer layer composition is substantially identical to the substrate composition. The presently disclosed methods further comprise epitaxially forming a heteroepitaxial layer on the buffer layer. The heteroepitaxial layer has a heteroepitaxial layer composition which is different from the substrate composition.

A super junction device with an increased voltage rating may be formed by creating a P liner on the sidewalls of a trench etched into N material, then filling the trench with additional N-type material. This thin P liner may be doped at a significantly higher concentration than the surrounding N material to maintain a charge balance. However, these relatively thin dimensions and the high doping concentration differential may cause P dopants to diffuse into the N material during subsequent high-temperature manufacturing processes. Diffusion barriers on either side of the P liner prevent diffusion of the dopants into the surrounding N material. The diffusion barriers create an abrupt interface between the N and P materials that prevents diffusion and improves the performance of the super junction devices.

A silicon carbide epitaxial substrate according to the present disclosure includes: a silicon carbide substrate; a first silicon carbide epitaxial layer disposed on the silicon carbide substrate; and a second silicon carbide epitaxial layer disposed on the first silicon carbide epitaxial layer. When an area density of first particles in the first silicon carbide epitaxial layer is defined as a first area density and an area density of second particles in the second silicon carbide epitaxial layer is defined as a second area density, a value determined by dividing the first area density by the second area density is more than 0.5 and less than 1. The first particles and the second particles each have a maximum diameter of 2 m to 50 m.

Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.

A method for forming an epitaxial stack on a plurality of substrates comprises providing a plurality of substrates to a process chamber and executing deposition cycles, wherein each deposition cycle comprises a first deposition pulse and a second deposition pulse. The epitaxial stack comprises a first epitaxial layer stacked alternatingly and repeatedly with a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer having a first native lattice parameter. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer having a second native lattice parameter, wherein the first native lattice parameter lies in a range within 1.5% larger than and 0.9% smaller than the second native lattice parameter.

Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.

Methods for fabricating SiC MOSFETs using compensating ion implants are disclosed. An n-type silicon carbide layer is epitaxially grown. After this growth process, a compensating ion implantation process is performed. This ion implantation process is used to compensate for the known dopant non-uniformity in the n-type silicon carbide layer. After the dopant concentration has been compensated, the traditional processes used to fabricate a planar SiC MOSFET may be performed. For super junction MOSFETs, the n-type epitaxial growth and compensating ion implantation processes may be repeated a plurality of times.