A semiconductor device includes a substrate, a source/drain pattern on the substrate, a gate structure on the substrate, an active contact connected to the source/drain pattern, a gate contact connected to the gate structure, and a wiring structure on the active contact, where the wiring structure includes a bridge wiring layer and a plurality of conductive wiring layers, the bridge wiring layer includes an active via connected to the active contact and a gate via connected to the gate contact, and each conductive wiring layer of the plurality of conductive wiring layers includes an active via connected to the active contact, a gate via connected to the gate contact, an active line on the active via of the respective conductive wiring layer, and a gate line on the gate via of the respective conductive wiring layer.

Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

A silicon carbide device including a trench contact structure configured to connect to a part of a transistor. The trench contact structure includes a trench having sidewalls, a silicide layer located in the trench and covering the sidewalls, and a metal contact element located in the trench and connected to the part of the transistor via the silicide layer.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A semiconductor die including a semiconductor substrate, an interconnect structure, a capacitor structure, a redistribution layer and a bonding structure is provided. The interconnect structure is disposed on the semiconductor substrate. The capacitor structure is disposed on the interconnect structure. The redistribution layer is disposed on and electrically connected to the interconnect structure. The bonding conductor is electrically and physically in contact with the capacitor structure at a sidewall of the bonding conductor, wherein the redistribution layer is located at a lower level than the bonding conductor.

A device may include a substrate comprising a plurality of first contact pads disposed on a first surface, and a plurality of second contact pads disposed on a second surface, the substrate comprising a plurality of interconnect structures extending between the first surface and the second surface. A device may include a first portion of an axial extension of the plurality of interconnect structures having sidewalls of a first profile. A device may include a second portion of the axial extension of the plurality of interconnect structures having sidewalls of a second profile, shallower than the first profile.

A semiconductor package including a first semiconductor chip, where the first semiconductor chip may include a first semiconductor layer, an upper wire structure located on the first semiconductor layer, an upper connection pad located on the upper wire structure, and a first upper conductive pattern located between the upper wire structure and the upper connection pad, where the first upper conductive pattern may include aluminum doped with a metallic material having a lower coefficient of thermal expansion than aluminum.