A semiconductor package includes a package substrate, a chip stack having first semiconductor chips stacked on the package substrate, a first molding film covering the chip stack on the package substrate, a first connection wire vertically penetrating the first molding film to be connected to the package substrate, and exposed onto an upper surface of the first molding film, a second semiconductor chip disposed on the first molding film, and having a first chip pad disposed on one surface facing the package substrate, a second molding film covering the second semiconductor chip on the first molding film, and a connection terminal connecting the first chip pad and an upper end of the first connection wire.

A semiconductor device according to the present invention includes a first conductive-type Sic semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface that is opposite to the first surface, a second semiconductor chip having a third surface facing the first surface and a fourth surface that is opposite to the third surface, a first dielectric layer on the first surface of the first semiconductor chip, a second dielectric layer on the third surface of the second semiconductor chip, a connection pad including a first conductive pad penetrating the first dielectric layer and a second conductive pad penetrating the second dielectric layer, and an adhesive layer between the first dielectric layer and the second dielectric layer, where the adhesive layer includes an organic dielectric material, the first conductive pad and the second conductive pad extend into the adhesive layer, and the first conductive pad directly contacts the second conductive pad.

A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

A semiconductor package is provided. The semiconductor package includes a first structure with a first insulating layer and a connection pad which penetrates through the first insulating layer; and a second structure with a second insulating layer bonded to the first insulating layer and a pad structure provided in a recess portion of the second insulating layer. The pad structure is bonded to and wider than the connection pad. The pad structure includes: an electrode pad disposed on a bottom surface of the recess portion; a solder disposed on the electrode pad and bonded to the connection pad; and a conductive support disposed to surround a side surface of the solder on the electrode pad and bonded to the first insulating layer. A melting point of the conductive support is higher than a melting point of the solder.

A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

Disclosed herein is an electronic component that includes: a substrate; a capacitor on the substrate; a first insulating resin layer embedding therein the capacitor; an inductor provided on the first insulating resin layer and connected to the capacitor, the inductor including a conductor pattern; a second insulating resin layer embedding therein the inductor; a third insulating resin layer on the second insulating resin layer; a post conductor having a lower end and an upper end and penetrating the third insulating resin layer such that the lower end of the post conductor is connected to the inductor; and a terminal electrode on the third insulating resin layer and connected to the upper end of the post conductor. In a thickness direction of the substrate, the height of the post conductor is larger than a thickness of a conductor pattern constituting the inductor.

A display device includes a substrate including a display area and a pad area; a first conductive layer including a first pad electrode in the pad area; and a second conductive layer the second conductive layer includes a second pad electrode on the first pad electrode in the pad area; the first pad electrode and the second pad electrode overlap in a first direction that is a thickness direction, and do not overlap in a second direction perpendicular to the first direction.

A semiconductor package includes a substrate having first and second surfaces opposite to each other in a vertical direction, a through electrode extending through the substrate and having an upper surface that is convex or concave, a protective pattern structure on the second surface of the substrate, and a conductive pad extending through the protective pattern structure. An upper portion of the conductive pad contacts an upper surface of the protective pattern structure. A lower portion of the conductive pad contacts an upper surface of the through electrode.